Designing a I2C slave using Spartan 3E and VHDL

Discussion in 'VHDL' started by LRCR, Dec 26, 2005.

  1. LRCR

    LRCR Guest

    I am designing a General IO controller with a I2C interface using a
    Spartan 3E. It seems simple since I2C slave needs to detect the start
    and end of a byte and reply with an acknowledge. Also, the FPGA I2C
    slave will use the master clock to read in the serial Bits. The first
    byte is the address and the second is the data. I am still a novice
    in VHDL and this is my first I2C project. I was told to do a VHDL
    generic design without buying an IP for this project. From my
    explanation of the design, I hope I am not missing anything. So far
    this is a Master to slave interface, but I am not sure if the reverse
    is require. But I want to start with a one direction interface first
    in order to get my feet wet in this type of interface. Can anyone
    suggest how I can start on the VHDL design. An outline or a sample
    code would be helpful
     
    LRCR, Dec 26, 2005
    #1
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