Detecting edge in a clock synchronous porcess

Discussion in 'VHDL' started by Praveen, Apr 12, 2005.

  1. Praveen

    Praveen Guest

    I have been using the following procedure to detect the edge of an
    signal in a clock synchronous process. I might have made some minor
    mistakes in the code below..but the concept is to use a temporary
    signal to detect the edge..

    Signal FlagTmp : std_logic;
    ...
    ...
    process(Reset,Clock)
    begin
    if (Reset = '0') then
    FlagTmp <= '1' ;
    elsif (Rising_edge (Clock)) then
    if(Mysignal = '1' and FlagTmp <= '1') then
    Output <= '1' ;
    FlagTmp <= '0' ;
    elsif (Mysignal = '0') then
    FlagTmp <= '1' ;
    Output <= '0' ;
    else
    Output <= '0' ;
    end if;
    end if;
    end process;

    I am not sure if this is a "grand" way of doing it. Could anyone
    suggest a better approach?

    Thanks.
     
    Praveen, Apr 12, 2005
    #1
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  2. Praveen wrote:
    > I have been using the following procedure to detect the edge of an
    > signal in a clock synchronous process. I might have made some minor
    > mistakes in the code below..but the concept is to use a temporary
    > signal to detect the edge..
    >
    > Signal FlagTmp : std_logic;
    > ..
    > ..
    > process(Reset,Clock)
    > begin
    > if (Reset = '0') then
    > FlagTmp <= '1' ;
    > elsif (Rising_edge (Clock)) then
    > if(Mysignal = '1' and FlagTmp <= '1') then
    > Output <= '1' ;
    > FlagTmp <= '0' ;
    > elsif (Mysignal = '0') then
    > FlagTmp <= '1' ;
    > Output <= '0' ;
    > else
    > Output <= '0' ;
    > end if;
    > end if;
    > end process;
    >
    > I am not sure if this is a "grand" way of doing it. Could anyone
    > suggest a better approach?


    Much simpler would be to think in hardware. It's just a flip-flop to get
    the previous value and a gate to detect prev_value = '0' and
    current_value = '1':

    signal my_sig_1d: std_logic;
    process
    begin
    wait until clock = '1';
    my_sig_1d <= my_sig;
    end process
    output <= my_sig and not my_sig_1d;

    Depending whether you put the signal assignment of output inside or
    outside the process you add and extra flip-flop (so an extra clock
    delay) or not.

    I've removed your asynchronous reset. You did not reset output anyway.

    Paul.
     
    Paul Uiterlinden, Apr 12, 2005
    #2
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  3. Praveen

    Bert Cuzeau Guest

    Praveen wrote:
    > I have been using the following procedure to detect the edge of an
    > signal in a clock synchronous process. I might have made some minor
    > mistakes in the code below..but the concept is to use a temporary
    > signal to detect the edge..
    >
    > Signal FlagTmp : std_logic;
    > ..
    > ..
    > process(Reset,Clock)
    > begin
    > if (Reset = '0') then
    > FlagTmp <= '1' ;
    > elsif (Rising_edge (Clock)) then
    > if(Mysignal = '1' and FlagTmp <= '1') then
    > Output <= '1' ;
    > FlagTmp <= '0' ;
    > elsif (Mysignal = '0') then
    > FlagTmp <= '1' ;
    > Output <= '0' ;
    > else
    > Output <= '0' ;
    > end if;
    > end if;
    > end process;
    >
    > I am not sure if this is a "grand" way of doing it. Could anyone
    > suggest a better approach?
    >
    > Thanks.
    >

    Not very far but...

    - Missing set/reset
    - missing resynchronization flip flop.

    Also: you didn't say "rising" but "edge".
    If it's any edge (<=> signal change) then use an xor.

    signal rDin, rrDin : std_logic;

    -- Synchronous edge detection
    process (Clk,Reset)
    begin
    if (Reset = '1') then
    rDIn <= '0';
    rrDin <= '0';
    Dout <= '0';
    elsif rising_edge(Clk) then
    rDIN <= Din;
    rrDin <= rDin;
    Dout <= rDin xor rrDin; -- any edge
    --Dout <= rDIn and not rrDin; -- rising etc...
    end if;
    end process;

    Beware of the possible spurrious detection at powerup if your signal
    is always '1'. (in which case you could preset instead of reset)

    Bert Cuzeau
     
    Bert Cuzeau, Apr 12, 2005
    #3
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