detecting keyboard strokes

Discussion in 'VHDL' started by aijazbaig1@gmail.com, Sep 4, 2006.

  1. Guest

    I am trying to write a program to scan the code generated by the
    keyboard corresponding to various keystrokes through an FPGA board. The
    project is now in an early development stage. I have written the code
    which does gets compiled but it seems to have a logical error.
    First of all, we need to have all the outputs of the keyboard
    synchronized with an on board sys_clk signal and then we need to read
    the data line during the falling edge of a particular signal also
    provided by the keyboard.
    Now what I've done is that I divided the tast into three processes.
    1. To get the imputs synchronized to the sys_clk.
    2. To detect the falling edge of the input signal kb_clk.
    3. To read the scan code and then generate an appropriate output.

    My Lab supervisor has provided a document which shows hows this is
    supposed to be done. It can be found here:
    http://www.es.isy.liu.se/courses/TSTE70/download/TSTE70_lab_kbd_060328.pdf
    ..

    And i've written the code for it which seem to have a logical error in
    it. I have declared a signal called detect_falling_kb_clk which goes to
    one for that entire period of sys_clk wherein the falling edge of the
    sys_clk has been detected. As the sys_clk is very fast compared to the
    kb_clk, it should appear as a pulse when compared to the kb_clk signal.
    However in my code it becomes '1' during the first detected edge and
    stays that way for the rest of the simulation time.
    I wonder if this has made my program malfunction.

    Heres the code :
    ************************************************************************************************************
    --
    -- VHDL Architecture lab1_lib.kbd_scanner.behavioral
    --
    -- Created:
    -- by - aijba273.student (olympen-11.edu.isy.liu.se)
    -- at - 09:26:02 09/04/06
    --
    -- using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
    --
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

    ENTITY kbd_scanner IS
    PORT(
    kb_clk : IN std_logic;
    kb_data : IN std_logic;
    sys_clk : IN std_logic;
    db : OUT std_logic_vector (7 DOWNTO 0);
    fcs : OUT std_logic;
    rlcs : OUT std_logic;
    rrcs : OUT std_logic;
    rsb : OUT std_logic_vector (6 DOWNTO 0);
    sdcs : OUT std_logic
    );

    -- Declarations

    -- Declarations

    type exemplar_string_array is array (natural range <>, natural range
    <>) of character;
    attribute pin_number : string;
    attribute array_pin_number : exemplar_string_array;
    attribute buffer_sig: string;
    attribute buffer_sig of sys_clk : signal is "IBUFG";
    attribute pin_number of sys_clk : signal is "P88";
    attribute pin_number of fcs : signal is "P41";
    attribute pin_number of rlcs : signal is "P79";
    attribute pin_number of rrcs : signal is "P80";
    attribute pin_number of sdcs : signal is "P132";
    attribute pin_number of kb_clk : signal is "P94";
    attribute pin_number of kb_data : signal is "P93";
    attribute array_pin_number of db : signal is ("P67", "P60", "P62",
    "P57", "P49", "P46", "P44",
    "P68");
    attribute array_pin_number of rsb : signal is ("P48", "P42", "P27",
    "P29", "P28", "P40",
    "P47");


    END kbd_scanner ;

    --
    ARCHITECTURE behavioral OF kbd_scanner IS
    signal temp_kb_clk : std_logic;
    signal temp_kb_data : std_logic;
    signal detect_falling_kb_clk : std_logic:= '0';
    signal scancode_barrel : std_logic_vector(9 downto 0);-- container for
    the whole 11 bit frame
    signal scancode : std_logic_vector(7 downto 0);
    begin
    fcs <= '1';
    rlcs <= '1';
    rrcs <= '1';
    sdcs <= '1';
    sync_keyboard : process(sys_clk) -- process to synchonize signals
    kb_clk and kb_data to sys_clk
    begin
    if sys_clk'EVENT and sys_clk = '1' then -- rising edge of the sys_clk
    detected
    temp_kb_clk <= kb_clk;
    temp_kb_data <= kb_data;
    end if;
    end process;

    dtct_falling_kb_clk : process(temp_kb_clk) -- process to detect the
    falling edge of synchronised kb_clk
    begin
    if temp_kb_clk'EVENT and temp_kb_clk = '0' then -- falling edge of
    the kb_clk detected
    detect_falling_kb_clk <= '1';
    end if;
    end process;


    convert_scancode : process(detect_falling_kb_clk)
    variable clk_cnt : integer := 0;
    begin
    if detect_falling_kb_clk = '1' then
    scancode_barrel <= kb_data&scancode_barrel(9 downto 1); -- for every
    rising edge of the detect falling edge signal,shift the data
    clk_cnt := clk_cnt + 1; -- bits in
    scancode_barrel to the right.do this 11 times
    if clk_cnt = 11 then
    db <= scancode_barrel(7 downto 0);
    -- db <= scancode;
    end if;
    end if;
    case scancode is
    when "00010110" => rsb <= "1101101";
    when "00011110" => rsb <= "0100010";
    when "00100110" => rsb <= "0100100";
    when "00100101" => rsb <= "1000101";
    when "00101110" => rsb <= "0010100";
    when "00110110" => rsb <= "0010000";
    when "00111101" => rsb <= "0101101";
    when "00111110" => rsb <= "0000000";
    when "01000110" => rsb <= "0000100";
    when "01000101" => rsb <= "0001000";
    when others => rsb <= "0010010";
    end case;
    end process;
    end Behavioral;

    *************************************************************************************************************
    Please provide some insight as to where Im going wrong so that I may
    correct them .

    Hoping to hear from you soon,
    , Sep 4, 2006
    #1
    1. Advertising

  2. wrote:

    > My Lab supervisor has provided a document which shows hows this is
    > supposed to be done. It can be found here:
    >

    http://www.es.isy.liu.se/courses/TSTE70/download/TSTE70_lab_kbd_060328.pdf
    > .


    Before letting read the whole world this text, read it yourself first.
    And if you claim to already have done that, do it again. You already
    have ignored the hint in 1.1.3.3. You should create just one
    synchronous process on sys_clk, not another one on temp_kb_clk.

    > And i've written the code for it which seem to have a logical error
    > in it. I have declared a signal called detect_falling_kb_clk which
    > goes to one for that entire period of sys_clk wherein the falling
    > edge of the sys_clk has been detected. As the sys_clk is very fast
    > compared to the kb_clk, it should appear as a pulse when compared to
    > the kb_clk signal. However in my code it becomes '1' during the
    > first detected edge and stays that way for the rest of the
    > simulation time.


    Of course if does. It does exactly what you have written. Where do you
    tell it to go low again?

    One final hint: don't regard VHDL as a programming language. Instead,
    look at it as a language describing hardware. Keep the hardware
    implementation in mind: where are the flip-flops? You should have an
    idea of that on forehand.

    --
    Paul.
    Paul Uiterlinden, Sep 4, 2006
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Andrew Clancy
    Replies:
    0
    Views:
    3,273
    Andrew Clancy
    Jul 18, 2003
  2. Keyvan Jamaleddin

    Keyboard Interface With Handshake

    Keyvan Jamaleddin, Aug 1, 2005, in forum: VHDL
    Replies:
    0
    Views:
    1,693
    Keyvan Jamaleddin
    Aug 1, 2005
  3. Pratap Das
    Replies:
    1
    Views:
    487
    Joe Smith
    May 8, 2004
  4. douha
    Replies:
    1
    Views:
    311
    Toby Inkster
    Jan 4, 2007
  5. abcd

    Capture key strokes

    abcd, Mar 1, 2007, in forum: Python
    Replies:
    0
    Views:
    259
Loading...

Share This Page