Determine entity/component port signal range

[Sven Heithecker]

Hi,

Is it possible to determine (or read, access) a enitiy/components port
signal range from "outside" ?
The ideas is that I declared an entity with a special port signal type:

entity test is
port(testsignal: in unsigned(5 downto 0));
end entity;

[component declaration omitted]

.... and now, in the architecture where I instantiate this entity, I want to
declare a signal which will be connected to the port, but I dont want to
specify the range again, so I tried something like:

achitecture rtl of test2 ist
signal: connected_to_testsignal: unsigned(test.testsignal'range);
^^^^^^^^^^^^^^^^^^^^^
begin
test_inst: test
port map(testsignal => connected_to_testsignal);

end rtl;

.... but that fails to compile. Is there a correct way, or is this simple my
compiler ?

I already searched the WWW and also the comp.lang.vhdl FAQ, but I didn't got
an answer, so I appeciate your help !

Thanx in andvance,
Sven Heithecker

--
Dipl.-Ing. Sven Heithecker
Institute of Computer and Communication Network Engineering
Technical University of Braunschweig, Germany
(e-mail address removed)-bs.de
www.ida.ing.tu-bs.de/~svenh

 

[Pieter Hulshoff]

Is it possible to determine (or read, access) a enitiy/components port
signal range from "outside" ?

Not in the way you described. Can you describe what you want to accomplish
with such a feature? Perhaps we can help you find the correct VHDL
construction(s) for the design idea you have.

Why would you want the signal definition to be depending on the size of the
port in the design? Is your port by any chance programmable in size? If so,
how (generic/package)?

Regards,

Pieter Hulshoff

 

[Ralf Hildebrandt]

entity test is
port(testsignal: in unsigned(5 downto 0));
end entity;

achitecture rtl of test2 ist
signal: connected_to_testsignal: unsigned(test.testsignal'range);

Why don't you use a generic parameter for the width (if the width should
be configurable)?

Ralf