different between !=0 and >0 in the net list level

Discussion in 'VHDL' started by Aiken, Feb 2, 2009.

  1. Aiken

    Aiken Guest

    if there is a counter counting from FF to 00, and input A and B.

    internal have a register

    if(A= '1')then
    register <= '0';
    elsif(B = '1' and counter >0) then
    register <= '1';
    end if;

    the above code, if I change to use != 0, then any difference in
    - Synthesis netlist
    - Speed or area
    Aiken, Feb 2, 2009
    #1
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  2. Aiken

    Tricky Guest

    On 2 Feb, 21:23, Aiken <> wrote:
    > if there is a counter counting from FF to 00, and input A and B.
    >
    > internal have a register
    >
    >      if(A= '1')then
    >         register <= '0';
    >       elsif(B = '1' and counter >0) then
    >         register <= '1';
    >       end if;
    >


    Best thing to do is try it. Different synthesisors may do different
    things, but they are usually quite clever. I wouldnt be surprised if
    they synthesised the same thing.

    What might be cheaper further though is:

    if B = '1' then
    if counter = 0 then
    register <= zero_state;
    else
    register <= '1';
    end if;
    end if;

    Checking a counter = 0 is much cheaper than any >, < etc. All you
    have to do is NOR all the bits together.


    > the above code, if I change to use != 0, then any difference in
    > - Synthesis netlist
    > - Speed or area


    As for this, I assume you meant /= 0 ;)
    Tricky, Feb 3, 2009
    #2
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  3. Aiken

    Andy Guest

    On Feb 3, 2:55 am, Tricky <> wrote:
    >
    > Checking a counter = 0 is much cheaper than any  >, < etc. All you
    > have to do is NOR all the bits together.


    Not necessarily..., > or < comparisons to a static 0 can be the same
    as, or even cheaper than = or /= comparisons. For instance, if count
    is signed, only one bit need be checked for < 0 (and none if count is
    and unsigned vector!). > 0 and /= 0 are usually optimized to the same
    circuit, but you should check your synthesis tool's performance just
    to make sure.

    One of the tricks of integer arithmetic synthesis is that expressions
    are promoted to 32 bit signed, no matter what the storage is (might be
    unsigned/natural). This means that even though count may be declared
    as a natural, count - 1 < 0 is a valid comparison, the arithmetic
    equivalent of = 0 for a down counter. Furthermore, most synthesis
    tools will recognize the decrement in the compare and the counter, and
    share the resources:

    variable count : natural range 0 to init;
    ....
    if count - 1 < 0 then -- check the carry bit
    do_something;
    count := init; -- roll over the counter
    else
    count := count - 1; -shared from comparison
    end if;

    Note: this will only work with integer (sub)types, NOT VECTOR TYPES.
    Operations on unsigned vectors return unsigned vectors, so (count - 1
    < 0) is always false if count is an unsigned vector.

    Don't worry, even though the integer decrement is promoted to 32 bits
    signed, stripping it down to N bits unsigned to fit in count will
    optimize out the extra bits (except the carry bit, and it is never
    stored).

    Andy
    Andy, Feb 3, 2009
    #3
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