Digital Counter Error

Discussion in 'VHDL' started by alextc1, Mar 27, 2013.

  1. alextc1

    alextc1

    Joined:
    Mar 27, 2013
    Messages:
    1
    Hi, I am new in FPGA, I have been trying to learn on the internet and the hours spent on FPGA learning is like 25 hours.

    I really would appreciate if someone could explain me some doubts that i have via Skype...

    This is a code for digital counter that i found on the internet but I dont know what is wrong and i have a lot of questions, an error on Implement design appear and it says this:

    Phase 12 : 0 unrouted; WARNING:Route:455 - CLK Net:clk_1Hz may have excessive skew because
    0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.


    The code is the next:

    -- Jim Duckworth
    -- ECE Dept, WPI
    -- January 6, 2005
    -- counter.vhd
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    entity counter is
    Port ( reset : in std_logic;
    clk_50M : in std_logic;
    seven_seg : out std_logic_vector(6 downto 0);
    an0 : out std_logic;
    led : out std_logic);
    end counter;

    architecture Behavioral of counter is

    component decoder is

    Port ( count : in integer range 0 to 9;
    seven_seg : out std_logic_vector(6 downto 0));
    end component;

    signal clk_1Hz : std_logic := '0'; -- define 1Hz clk and start value (for simulation)
    signal count : integer range 0 to 9;

    begin
    -- make a copy of the decoder component
    decoder1: decoder port map (count => count, seven_seg => seven_seg);
    -- generate a 1 second clock from the 50MHz oscillator
    one_second_process: process(reset, clk_50M)
    variable counter_50M : integer range 0 to 25_000_000;

    begin

    if reset = '1' then
    counter_50M := 0;

    elsif rising_edge(clk_50M) then
    counter_50M := counter_50M + 1;

    if counter_50M = 25_000_000 then
    clk_1Hz <= NOT clk_1Hz;
    counter_50M := 0;

    end if;
    end if;
    end process one_second_process;

    -- count seconds from 0 to 9
    count_process: process(reset, clk_1Hz)

    begin
    if reset = '1' then
    count <= 0;

    elsif rising_edge(clk_1Hz) then
    if count = 9 then
    count <= 0;
    else
    count <= count + 1;
    end if;
    end if;
    end process count_process;

    an0 <= '0'; -- just keep anode0 on
    led <= '1' when count = 9 else '0';
    end Behavioral;


    and the second program is this:

    -- Jim Duckworth
    -- ECE Dept, WPI
    -- January 6, 2005
    -- decoder.vhd
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    entity decoder is
    Port ( count : in integer range 0 to 9;
    seven_seg : out std_logic_vector(6 downto 0));
    end decoder;
    architecture Behavioral of decoder is
    constant zero : std_logic_vector(6 downto 0) := "1000000";
    constant one : std_logic_vector(6 downto 0) := "1111001";
    constant two : std_logic_vector(6 downto 0) := "0100100";
    constant three : std_logic_vector(6 downto 0) := "0110000";
    constant four : std_logic_vector(6 downto 0) := "0011001";
    constant five : std_logic_vector(6 downto 0) := "0010010";
    constant six : std_logic_vector(6 downto 0) := "0000010";
    constant seven : std_logic_vector(6 downto 0) := "1111000";
    constant eight : std_logic_vector(6 downto 0) := "0000000";
    constant nine : std_logic_vector(6 downto 0) := "0010000";
    begin
    --display the count value on the seven segments
    seven_segment_decoder_process: process(count)
    begin
    case count is
    when 0 => seven_seg <= zero;
    when 1 => seven_seg <= one;
    when 2 => seven_seg <= two;
    when 3 => seven_seg <= three;
    when 4 => seven_seg <= four;
    when 5 => seven_seg <= five;
    when 6 => seven_seg <= six;
    when 7 => seven_seg <= seven;
    when 8 => seven_seg <= eight;
    when 9 => seven_seg <= nine;
    end case;
    end process seven_segment_decoder_process;
    end Behavioral;


    can anyone help me please, i have Skype user: alextowers1

    Thanks!!
    alextc1, Mar 27, 2013
    #1
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