Dilemna w/ generic port of type array of slv

Discussion in 'VHDL' started by Brandon, Aug 4, 2005.

  1. Brandon

    Brandon Guest

    Hopefully I'm not being stupid here but...
    I'm trying to create a shift register with parallel outputs, but
    because I want it to have a generic word width and shift length, it
    seems slightly tricky to me. I can't use an array of std_logic_vector,
    as that would mean an unconstrained array of an unconstrained array.
    Instead, I can unwrap the array and create:

    x: std_logic_vector(width*length-1 downto 0).

    This doesn't naturally lend itself to indexing and/or simulation and
    display, so I figured I'd come up with a function to convert 'x'

    to a type:

    array (length-1 downto 0) of std_logic_vector(width-1 downto 0)

    However, I realized I can't do this, because this would involve
    returning an unconstrained array of unconstrained array type. So, is
    this the best solution to access individual words?

    x(i) <= std_logic_vector( (i+1)*width-1 downto i*width);
    -- where i = 7 downto 0

    If anyone has any cleaner methods I'd love to hear them...
    Thanks.
     
    Brandon, Aug 4, 2005
    #1
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  2. Brandon

    woko Guest

    TYPES could solve your problem. Here is some expamle code from a
    current project:

    constant cAIN : integer := 59; -- 0 - cADC_CH
    type TAIN is record
    Value : std_logic_vector (11 downto 0);
    end record;
    type TAIN_ALL is array (cAIN downto 0) of TAIN;

    signal Ain : TAIN_ALL;

    Ain(1).Value(7 downto 0) <= X"13";

    Maybe you can arrange it for your purpose.
    Cheers,
    Wolfgang Kopp
     
    woko, Aug 5, 2005
    #2
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  3. Hard to figure out what exactly your trying to do from the above code
    particularly the following line since there is no signal on the
    right-hand side that I can tell:

    x(i) <= std_logic_vector( (i+1)*width-1 downto i*width);

    Is shift_length a siganal or generic constant. Are you doing circular
    shifting, right shifting, or left shifting.

    Sometime one can use for generate loops with nested if generates to
    build all possible cases and remove the unconstrained-ness.
     
    combinational.logic $ soc-ip.com, Aug 5, 2005
    #3
  4. Brandon

    Brandon Guest

    Maybe my wording was confusing, but this is essentially what I want in
    my serial in, parallel output shift register:

    <SNIP>
    library ieee;
    use ieee.std_logic_1164.all;

    entity srsipo is
    generic (
    dlength_g : integer; -- shifter length
    dwidth_g : integer; -- word size
    tpd_g : time := 0 ns
    );
    port (

    -----------------------------------------------------------------------
    -- input
    --------------------------------------------------------------
    clk : in std_logic;
    rst_n_a : in std_logic;
    den : in std_logic;
    d : in std_logic;
    -- output
    -------------------------------------------------------------
    q : out ??????

    -----------------------------------------------------------------------
    );
    end entity srsipo;
    </SNIP>

    I'd like to have both the shift register length and word size to be
    generics. I can't have an array of std_logic on the port q because it
    would be unconstrained, i.e. I'd need a type as follows:

    q: out array (dlength_g-1 downto 0) of std_logic_vector(dwidth_g-1
    downto 0)

    I can't do that, because I'd have to define a type for that. I can't
    define the type (in a package, for example) because I need visibility
    of the generics first.

    So instead I'll have to do:

    q: out std_logic_vector(dlength_g*dwidth_g-1 downto 0)

    The problem here is that I can't access the words in a natural way. But
    I could do something like:

    x(i) <= q( (i+1)*width-1 downto i*width);

    Which isn't nearly as easy to comprehend in code or simulation as:

    y(i) <= q(i); -- Where q would be an array slv

    Do I have any other options here?
    Thanks...
     
    Brandon, Aug 5, 2005
    #4
  5. Brandon

    Brandon Guest

    Ooops, the input data port, d should be:

    d: in std_logic_vector(dwidth_g-1 downto 0);
     
    Brandon, Aug 5, 2005
    #5
  6. As I recall arrays with generics on port definitions are a no-no for
    synthesis. What I normally do is keep the ports as single dimension
    std_logic_vectors. I refer to these as bundles -- they are essentially
    a collapsed array.

    Then in the architecture declare a signal that is an array of the type
    you desire. Then map the bundle into the array signal in your
    architecture (using a generate loop). Do all your processing on the
    array. Then for your output signal you will need to map the array back
    into a bundle.

    Your simulator should let you probe the internal arrays.

    Hope this helps.
     
    combinational.logic $ soc-ip.com, Aug 6, 2005
    #6
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