dimension of an integer

Discussion in 'VHDL' started by Max, Sep 19, 2003.

  1. Max

    Max Guest

    How can I obtain the dimension in bit of an integer?

    I have a generic, and I need to store its value in a std_logic_vector,
    but I don't know the dimansion of this vector.

    thanks
     
    Max, Sep 19, 2003
    #1
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  2. Max wrote:
    >
    > How can I obtain the dimension in bit of an integer?
    >
    > I have a generic, and I need to store its value in a std_logic_vector,
    > but I don't know the dimansion of this vector.
    >
    > thanks


    Maybe you can use attributes such as 'high and 'low etc?
    --
    ===================================================================
    Johan Wouters === Easics NV
    Senior ASIC designer === a TranSwitch Company
    Tel: +32-16-395 616 === System-on-Chip Design
    Fax: +32-16-395 619 Interleuvenlaan 86, B-3001 Leuven, BELGIUM
    mailto: http://www.easics.com
     
    Johan Wouters, Sep 19, 2003
    #2
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  3. Max

    Jim Lewis Guest

    Assignments to unconstrained integer signals typically
    result in 32 bit signed hardware.

    For synthesis, I only recommend using integers
    as literal values numeric expressions:
    Y <= '1' when A > 12 else '0' ;
    Count <= Count + 1 ;

    In this case you don't need any conversions, it
    works because of the overloading.


    For a quick tutorial on VHDL overloading, conversions, ... see my
    MAPLD paper, VHDL Math Tricks of the Trade. It is available
    at http://www.synthworks.com/papers

    Cheers,
    Jim Lewis
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


    Max wrote:

    > How can I obtain the dimension in bit of an integer?
    >
    > I have a generic, and I need to store its value in a std_logic_vector,
    > but I don't know the dimansion of this vector.
    >
    > thanks
     
    Jim Lewis, Sep 19, 2003
    #3
  4. On Fri, 19 Sep 2003 09:03:13 -0700, Jim Lewis <>
    wrote:

    >Assignments to unconstrained integer signals typically
    >result in 32 bit signed hardware.


    Max was asking how to determine the range for an slv that would hold
    an integer of a particular value.

    http://groups.google.com/groups?as_q=log2&as_ugroup=comp.lang.vhdl

    Regards,
    Allan.
     
    Allan Herriman, Sep 22, 2003
    #4
  5. Max

    sean Guest

    (Max) wrote in message
    > How can I obtain the dimension in bit of an integer?
    >
    > I have a generic, and I need to store its value in a std_logic_vector,
    > but I don't know the dimansion of this vector.
    >


    If you use the CONV_STD_LOGIC_VECTOR function in std_logic_arith you
    specify the number of bits for the resulting vector, eg

    CONV_STD_LOGIC_VECTOR(5, 4) returns a 4-bit vector "0101"

    Other conversion functions have the same arguments.

    If you want an integer-type signal to be synthesised with a certain
    number of bits, you define the range when you declare the signal, eg

    signal blahblah : integer range 0 to 15; will synthesise to a 4 bit
    signal.

    Sean
     
    sean, Sep 22, 2003
    #5
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