Assignments to unconstrained integer signals typically
result in 32 bit signed hardware.
For synthesis, I only recommend using integers
as literal values numeric expressions:
Y <= '1' when A > 12 else '0' ;
Count <= Count + 1 ;
In this case you don't need any conversions, it
works because of the overloading.
For a quick tutorial on VHDL overloading, conversions, ... see my
MAPLD paper, VHDL Math Tricks of the Trade. It is available
at
http://www.synthworks.com/papers
Cheers,
Jim Lewis
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Jim Lewis
Director of Training mailto:
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SynthWorks Design Inc.
http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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