direct instantiation, libraries

Discussion in 'VHDL' started by valentin tihomirov, Apr 23, 2004.

  1. Here is synthax:
    label : entity lib_name.entity_name(architecture_name) port map (.....);

    The problem is to use any different library rather than 'work'. Even
    simulator refuses to compile this:

    -- declare libs
    library IEEE, LibraryA, LibraryB;

    use IEEE.STD_LOGIC_1164.ALL;

    --interface
    entity MULTILIB_DESIGN is
    port (
    A, B: in std_logic;
    O : out std_logic
    );
    end MULTILIB_DESIGN;

    --implementation
    architecture RTL of AND2 is
    signal AND_O, XOR_O: std_logic;
    begin
    AND_U: entity libraryA.AND2(RTL) port map (A, B, AND_O); -- Unknown
    identifier LibraryA
    XOR_U: entity libraryB.XOR2(RTL) port map (A, B, XOR_O);-- Unknown
    identifier LibraryB
    O <= AND_O or XOR_O;
    end RTL;

    As far as I can understand, the idea of libraries is to isolate primitives
    into namespaces. This is what I want to achieve. The VHDL must be
    synthesizable.
    valentin tihomirov, Apr 23, 2004
    #1
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  2. valentin tihomirov wrote:

    > The problem is to use any different library rather than 'work'. Even
    > simulator refuses to compile this:


    The mapping from vhdl library identifier to
    a physical directory is a tool setting, not part of the language.
    The only directory not needing a mapping is ./work

    For modelsim, the command is vmap.
    Every tool is different.
    See:

    http://groups.google.com/groups?q=vhdl vmap vlib work

    -- Mike Treseler
    Mike Treseler, Apr 24, 2004
    #2
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  3. Simulator is aware of libraryA and libraryB. I'm asking whether VHDL usage
    is correct? I have not met any example using lib_name in the component
    instantiation.
    valentin tihomirov, Apr 24, 2004
    #3
  4. valentin tihomirov wrote:

    > Simulator is aware of libraryA and libraryB. I'm asking whether VHDL usage
    > is correct?


    Yes. If the mappings are correct, perhaps the entities were not
    compiled into the correct directories.

    -- Mike Treseler
    Mike Treseler, Apr 24, 2004
    #4
  5. Thanks, I make a conclusion that vendors have poor support of using library
    identifier in component instantiation. Entities are precompiled into
    separate libraryies and "unknown library" error message is shown.
    valentin tihomirov, Apr 25, 2004
    #5
  6. valentin tihomirov

    David Jones Guest

    In article <c6g4pv$blqcl$-berlin.de>,
    valentin tihomirov <> wrote:
    >Thanks, I make a conclusion that vendors have poor support of using library
    >identifier in component instantiation. Entities are precompiled into
    >separate libraryies and "unknown library" error message is shown.
    >
    >


    The syntax

    U1: somelib.acell(rtl) port map(
    ...
    )

    is new to VHDL-93. If you are using a tool such as ModelSim that defaults
    to VHDL-87, then you will need to supply the correct compiler flag to
    get it to accept VHDL-93.
    David Jones, Apr 26, 2004
    #6
  7. Yess! I've got to compile it in ActiveHDL and then in Sinplify. The problem
    was misleading error message caused by architecture name declatation.
    ActiveHDL compiles 93 synthax by default. Furthermore, it allows setting
    library for each VHDL file and one-click synthsis. Sinplify compiles without
    problems. As usually, I'm getting problems with XST. Webpack environment
    assigns VHDL files to correct libraries but I'm getting hierarchy error on
    project load. Possibly, this is question to Xilinx support:


    -------------------- libraryA----------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    entity AND2 is
    port (
    A, B: in std_logic;
    O : out std_logic
    );
    end AND2;
    architecture RTL of AND2 is
    begin
    O <= A and B;
    end RTL;


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    entity OR2 is
    port (
    A, B: in std_logic;
    O : out std_logic
    );
    end OR2;
    architecture RTL of OR2 is
    begin
    O <= A or B;
    end RTL;
    -------------------- end libraryA----------------


    -------------------- libraryB----------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity XOR2x is
    port (
    A, B: in std_logic;
    O : out std_logic
    );
    end XOR2x;

    architecture RTL of XOR2x is
    begin
    O <= A xor B;
    end RTL;


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    entity OR2 is
    port (
    A, B: in std_logic;
    O : out std_logic
    );
    end OR2;
    architecture RTL of OR2 is
    begin
    O <= A or B;
    end RTL;

    -------------------- end libraryB----------------



    -------------------- library work----------------
    library IEEE, LibraryA, LibraryB;
    use IEEE.STD_LOGIC_1164.ALL;

    entity MULTILIB_DESIGN is
    port (
    A, B: in std_logic;
    O : out std_logic
    );
    end MULTILIB_DESIGN;

    architecture RTL of MULTILIB_DESIGN is
    signal AND_O, XOR_O: std_logic;
    begin
    AND_U: entity libraryA.AND2 port map (A, B, AND_O);
    XOR_U: entity libraryB.XOR2x port map (A, B, XOR_O);
    O <= AND_O or XOR_O;
    end RTL;
    -------------------- end library work----------------
    valentin tihomirov, Apr 26, 2004
    #7
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