Disconnect instantiation during Simulation

Discussion in 'VHDL' started by Shanmugavel D, Aug 4, 2008.

  1. Dear All,

    In my test bench, I have written my test cases as packages, Some of my
    test cases requires three instantiation of DUT, some test cases
    requires only one DUT and some requires two.

    Since am using three RTLs Simulation taking more time.

    I am not able to vary the n.o. of instantiation by using "generate",
    because after the instantiation only test cases are called.

    Is there any way to disconnect the Instantion during simulation?

    Thanks in advance.

    Best Regards,
    Shanmugavel D
     
    Shanmugavel D, Aug 4, 2008
    #1
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  2. Shanmugavel D

    Andy Guest

    On Aug 4, 7:36 am, Shanmugavel D <> wrote:
    > Dear All,
    >
    > In my test bench, I have written my test cases as packages, Some of my
    > test cases requires three instantiation of DUT, some test cases
    > requires only one DUT and some requires two.
    >
    > Since am using three RTLs Simulation taking more time.
    >
    > I am not able to vary the n.o. of instantiation by using "generate",
    > because after the instantiation only test cases are called.
    >
    > Is there any way to disconnect the Instantion during simulation?
    >
    > Thanks in advance.
    >
    > Best Regards,
    > Shanmugavel D


    The test bench that calls the test cases should be able to set the
    value of a constant that can drive a generate statement to instantiate
    the correct number of DUTs. Otherwise, top level generics can be set
    by command line options on most tools. Such a generic could be passed
    down to the appropriate level to drive a generate statement that
    instantiates the correct number of DUTs.

    Andy
     
    Andy, Aug 4, 2008
    #2
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