H
hssig
Hi,
I have the following VHDL case structure:
signal numa : unsigned(2 downto 0);
constant cA : unsigned(2 downto 0) := "000";
constant cB : unsigned(2 downto 0) := "001";
constant cC : unsigned(2 downto 0) := "100";
process(rstn, clk)
begin
if rstn='0' then
numa <= "000";
elsif rising_edge(clk) then
...
case to_integer(numa) is
when to_integer(cA) => ...
when to_integer(cB) to to_integer(cC) => ...
when others => ...
end case;
end if;
end process;
When trying to insert a (Lattice) Reveal core I get the following
error message:
"ERROR: case choice must be a locally static expression (VHDL-1438)"
How can I make use of the discrete range choice without violating the
static expression rule ?
Thank you for your opinion.
Cheers,
hssig
I have the following VHDL case structure:
signal numa : unsigned(2 downto 0);
constant cA : unsigned(2 downto 0) := "000";
constant cB : unsigned(2 downto 0) := "001";
constant cC : unsigned(2 downto 0) := "100";
process(rstn, clk)
begin
if rstn='0' then
numa <= "000";
elsif rising_edge(clk) then
...
case to_integer(numa) is
when to_integer(cA) => ...
when to_integer(cB) to to_integer(cC) => ...
when others => ...
end case;
end if;
end process;
When trying to insert a (Lattice) Reveal core I get the following
error message:
"ERROR: case choice must be a locally static expression (VHDL-1438)"
How can I make use of the discrete range choice without violating the
static expression rule ?
Thank you for your opinion.
Cheers,
hssig