Discussion "Async Reset"

Discussion in 'VHDL' started by ALuPin, Oct 25, 2004.

  1. ALuPin

    ALuPin Guest

    Hi @ all,

    I have read the discussion "Async Reset".

    There it has been mentioned that it is one possibility to
    synchronize an asynchronous reset so that all flip flops in
    the FPGA are resetted within the same clock period.

    Using this synchronized reset
    can I still write the process like that:


    process(Sync_reset, Clk)
    begin
    if Sync_reset='1' then
    ...
    elsif rising_edge(Clk) then
    ...
    end if;

    end process;

    or does it make more sense to write it like that:

    process(Sync_reset, CLk)
    begin
    if rising_edge(Clk) then
    if Sync_reset='1' then
    ...
    else
    ...
    end if;
    end if;
    end process;

    I would be very thankful for your opinion.

    Rgds
    André
     
    ALuPin, Oct 25, 2004
    #1
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  2. ALuPin

    Element Blue Guest

    On Mon, 25 Oct 2004, ALuPin wrote:

    > Hi @ all,
    >
    > I have read the discussion "Async Reset".
    >
    > There it has been mentioned that it is one possibility to
    > synchronize an asynchronous reset so that all flip flops in
    > the FPGA are resetted within the same clock period.
    >
    > Using this synchronized reset
    > can I still write the process like that:
    >
    >
    > process(Sync_reset, Clk)
    > begin
    > if Sync_reset='1' then
    > ...
    > elsif rising_edge(Clk) then
    > ...
    > end if;
    >
    > end process;
    >
    > or does it make more sense to write it like that:
    >
    > process(Sync_reset, CLk)
    > begin
    > if rising_edge(Clk) then
    > if Sync_reset='1' then
    > ...
    > else
    > ...
    > end if;
    > end if;
    > end process;
    >
    > I would be very thankful for your opinion.


    The latter is a synchronous reset,i.e,FFs will reset ON the clock edge.
    The former is asynchronous reset,which can be synchronized to the clock
    edge to reset all FFs within a clock period,and to avoid setup/hold
    conditions which arise when a async reset goes active "close" to clock
    edge.So,if the reset signal is being syncronized to the clock externally,
    both processes will work ok,else only the second process guarantees a
    synchronous reset (which will reset FFs within the cycle).In the first
    process,the reset happens whenever the Sync_reset goes high, and you
    should ensure that it doesnt happen close to clock edge.
    Hope that helps,
    EB.

    >
    > Rgds
    > André
    >
     
    Element Blue, Oct 25, 2004
    #2
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  3. ALuPin

    Raghavendra Guest

    (ALuPin) wrote in message news:<>...
    > Hi @ all,
    >
    > I have read the discussion "Async Reset".
    >
    > There it has been mentioned that it is one possibility to
    > synchronize an asynchronous reset so that all flip flops in
    > the FPGA are resetted within the same clock period.
    >
    > Using this synchronized reset
    > can I still write the process like that:
    >
    >
    > process(Sync_reset, Clk)
    > begin
    > if Sync_reset='1' then
    > ...
    > elsif rising_edge(Clk) then
    > ...
    > end if;
    >
    > end process;
    >
    > or does it make more sense to write it like that:
    >
    > process(Sync_reset, CLk)
    > begin
    > if rising_edge(Clk) then
    > if Sync_reset='1' then
    > ...
    > else
    > ...
    > end if;
    > end if;
    > end process;
    >
    > I would be very thankful for your opinion.
    >
    > Rgds
    > André


    HI,
    To avoid problems with asynchronous reset you can have asynchronous
    reset assert and synchronous dessert using synchronizers.
    Raghavendra.Sortur
     
    Raghavendra, Oct 27, 2004
    #3
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