Display Control Application Using Spartan FPGA

[Maurice Branson]

Hi folks,

I have been introduced to a project where I have to implement a TFT display
controlller on a low-cost FPGA like Spartan-3 or Spartan-6. The controller
has to support at least XGA - 1024x768, SXGA - 1280x1024, UXGA - 1600x1200
and WUXGA 1920x1200. I have to chose an appropriate platform now. As I am a
total newbie in the field of image processing on FPGAs I would ask you for
your recommendation about size and type of FPGA, especially in terms of
logic for video scaling and SRAM memories for frame buffer storage.

Many thanks in advance.

KR, Maurice

 

[Gabor]

Hi folks,

I have been introduced to a project where I have to implement a TFT display
controlller on a low-cost FPGA like Spartan-3 or Spartan-6. The controller
has to support at least XGA - 1024x768, SXGA - 1280x1024, UXGA - 1600x1200
and WUXGA 1920x1200. I have to chose an appropriate platform now. As I am a
total newbie in the field of image processing on FPGAs I would ask you for
your recommendation about size and type of FPGA, especially in terms of
logic for video scaling and SRAM memories for frame buffer storage.

Many thanks in advance.

KR, Maurice

Depending on how much processing you do, you might find that you're
actually limited in choice by the number of I/O's you need rather
than the fabric capacity of the part. The family choice probably
depends on your interface speed. If you need Panel-Link at high
data rates, for example you probably want to look at newer parts.
Most video designs use SDRAM for frame buffer, as there is no
speed penalty when the bulk of your access is sequential, and
latency is almost never an issue. DDR2 works well without all
the external terminating components or Vtt supply if you can
use just one or two parts and keep the routes down around an
inch. For scaling it's best to pick a family with built-in
multipliers, but again since latency is usually not an issue,
you could build multipliers from the fabric as long as you
pipeline them enough to run at speed. The number of multipliers
depends to some extent on the maximum scaling ratio, because
you'll need to build better filters for higher scaling ratios
(more taps). At small scaling ratios, like 1.2:1 for example,
you can probably ditch the filters and just use interpolation.
HTH,
Gabor

 

[rickman]

Hi folks,

I have been introduced to a project where I have to implement a TFT display
controlller on a low-cost FPGA like Spartan-3 or Spartan-6. The controller
has to support at least XGA - 1024x768, SXGA - 1280x1024, UXGA - 1600x1200
and WUXGA 1920x1200. I have to chose an appropriate platform now. As I am a
total newbie in the field of image processing on FPGAs I would ask you for
your recommendation about size and type of FPGA, especially in terms of
logic for video scaling and SRAM memories for frame buffer storage.

Many thanks in advance.

KR, Maurice

Build your controller design and measure the size to pick the part you
need. Anything else is speculation without a clear understanding of
the design.

BTW, a display controller is not "image processing". It is just a
display controller. If you need to do image processing, you need to
describe that in detail to include in your size estimate.

Rick

 

[Raymund Hofmann]

I have been introduced to a project where I have to implement a TFT display
controlller on a low-cost FPGA like Spartan-3 or Spartan-6. The controller
has to support at least XGA - 1024x768, SXGA - 1280x1024, UXGA - 1600x1200
and WUXGA 1920x1200. I have to chose an appropriate platform now. As I am a
total newbie in the field of image processing on FPGAs I would ask you for
your recommendation about size and type of FPGA, especially in terms of
logic for video scaling and SRAM memories for frame buffer storage.

From my pesonal experience of porting my display contol / scaler ASIC
to a FPGA i would recommend Lattice ECP2/3. I think their timing
Performance is significantly better than Spartan 3 making it not too
difficult to achieve the timing you need for what you say.
But it looks like all this could keep you busy for a few years as a
"total newbie".

 

[John Adair]

The starting point for this is storage for data and the bandwidth to
access it. For those reasons I would suggest our Drigmorn3 as a
starting point with 1Gbit of DDR3. The advantage of the DDR3 is
density and speed.

For the manipulation there will be a big difference between possible
control/processing engines and it is difficult to be accurate of what
size is best. The LX16 on the Drigmorn3 is a reasonable size but if
you think that is not enough there will be another product shortly
with a bigger part.

John Adair
Enterpoint Ltd. - Home of Merrick1. The HPC Solutions.

 

[drewnity]

FPGA Based Signal Generator

Hello!

I don't know why I can't post a new thread yet but anyway, am wondering if any of you would be able to help me with the title above? I'm trying to generate signal driven by the 50Mhz clock on the Altera DE2 Board with a factor divide by 3. I have already done a design divide by 2. Is there idea? Apart from that, I'm trying to use the push buttons to toggle my frequency up and down using a counter. I'm not too sure how to do it coz I'm new to this. Pls guide! Thanks!