Displaying signals internal to the architecture part of an entity

Discussion in 'VHDL' started by aijazbaig1@gmail.com, Sep 2, 2006.

  1. Guest

    Hello,
    I am trying to write a code to scan the code generated by the keyboard
    through an FPGA board. The project is now in an early development
    stage.
    Heres the most basic process in which I try to synchronise the inputs
    to the system viz. kb_clk and data to the on board 'sys_clk', the
    system clk.
    heres the code ive written,

    Library ieee;

    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_unsigned.all;

    entity code_test_process1 is
    port(
    kb_clk : IN std_logic;
    data : IN std_logic_vector(7 downto 0));
    end code_test_process1;

    architecture trial1 of code_test_process1 is
    signal sys_clk : std_logic;
    signal current_kbclk : std_logic;
    signal current_data : std_logic_vector(7 downto 0);
    begin
    process(sys_clk)
    begin
    if rising_edge(sys_clk) then
    current_kbclk <= kb_clk;
    current_data <= data;
    end if;
    end process;
    end trial1;

    the test bench file for the above program is here:
    library work;
    Library ieee;

    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_unsigned.all;
    use work.all;

    entity test_bench is
    begin
    end test_bench;

    architecture test of test_bench is
    signal kb_clk,sys_clk : std_logic;
    signal data : std_logic_vector(7 downto 0);
    component code_test_process1 is
    port(
    kb_clk : IN std_logic;
    data : IN std_logic_vector(7 downto 0));
    end component code_test_process1;
    for all:code_test_process1 use entity
    work.code_test_process1(trial1);
    begin
    P1:code_test_process1 port map(kb_clk => kb_clk,data =>
    data);
    process
    begin
    data <= X"10" after 100 ns,X"08" after 200
    ns,X"A2" after 300 ns,X"2F" after 400 ns,X"11" after 500 ns,X"3C" after
    600 ns;
    sys_clk <= '1' after 150 ns,'0' after 250 ns,'1'
    after 420 ns,'0' after 475 ns,'1' after 550 ns,'1' after 570 ns;
    kb_clk <= '1' after 50 ns,'0' after 100 ns,'1'
    after 150 ns,'0' after 200 ns,'1' after 250 ns,'0' after 300 ns,'1'
    after 350 ns,'0' after 400 ns,'1' after 450 ns,'0' after 500 ns,'1'
    after 550 ns,'0' after 600 ns;

    wait;
    end process;
    end test;

    What I don't understand now is how do I display the contents of the
    signals current_kbclk and current_data which are internal to the entity
    code_test_process1 so that I may check if the inputs are sampled only
    at sys_clk or not. How do I display those signals as well on the wave?

    Best Regards,
    Aijaz Baig.
     
    , Sep 2, 2006
    #1
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  2. Frank Buss Guest

    wrote:

    > process
    > begin
    > data <= X"10" after 100 ns,X"08" after 200
    > ns,X"A2" after 300 ns,X"2F" after 400 ns,X"11" after 500 ns,X"3C" after
    > 600 ns;
    > sys_clk <= '1' after 150 ns,'0' after 250 ns,'1'
    > after 420 ns,'0' after 475 ns,'1' after 550 ns,'1' after 570 ns;
    > kb_clk <= '1' after 50 ns,'0' after 100 ns,'1'
    > after 150 ns,'0' after 200 ns,'1' after 250 ns,'0' after 300 ns,'1'
    > after 350 ns,'0' after 400 ns,'1' after 450 ns,'0' after 500 ns,'1'
    > after 550 ns,'0' after 600 ns;


    You could simplify this, e.g. for a test bench for the 1-wire protocol of
    http://www.frank-buss.de/vhdl/spartan3e.html I've used a loop:

    constant rom_test: unsigned(63 downto 0) := x"cf000000e4ec2933";
    ....
    test_loop: process
    variable rom: unsigned(63 downto 0);
    begin
    ....
    -- simulate ROM result
    rom := rom_test;
    for j in 1 to 64 loop
    wait until ds_wire = '0';
    wait until ds_wire = 'Z';
    if rom(0) = '0' then
    ds_wire <= '0';
    wait for 30 us;
    ds_wire <= 'Z';
    wait for 1 us;
    end if;
    rom := shift_right(rom, 1);
    end loop;
    ....

    > What I don't understand now is how do I display the contents of the
    > signals current_kbclk and current_data which are internal to the entity
    > code_test_process1 so that I may check if the inputs are sampled only
    > at sys_clk or not. How do I display those signals as well on the wave?


    This depends on the program you are using. With ActiveHDL you simply
    drag-and-drop all signals to the wave form window, including internal
    signals from sub entities.

    --
    Frank Buss,
    http://www.frank-buss.de, http://www.it4-systems.de
     
    Frank Buss, Sep 2, 2006
    #2
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  3. Guest

    Hello.
    I was able to add those two signals to the wave window by using the
    command line version command
    add wave/test_bench/p1/* which adds all the signals within the
    component instantiation P1. Now I seem to have a different problem. In
    my test_bench entity(i.e. in the architecture part) I have made sys_clk
    work like a clock for a specified period of time. It isn't showing up
    on the wave window when I simulate for about 600 ns.
    Only the signals data and kb_clk seem to get updated with some values.
    Not even sys_clk gets updated with the values I supplied.
    Would you let me know where am I going wrong here.
    Frank Buss wrote:
    > wrote:
    >
    > > process
    > > begin
    > > data <= X"10" after 100 ns,X"08" after 200
    > > ns,X"A2" after 300 ns,X"2F" after 400 ns,X"11" after 500 ns,X"3C" after
    > > 600 ns;
    > > sys_clk <= '1' after 150 ns,'0' after 250 ns,'1'
    > > after 420 ns,'0' after 475 ns,'1' after 550 ns,'1' after 570 ns;
    > > kb_clk <= '1' after 50 ns,'0' after 100 ns,'1'
    > > after 150 ns,'0' after 200 ns,'1' after 250 ns,'0' after 300 ns,'1'
    > > after 350 ns,'0' after 400 ns,'1' after 450 ns,'0' after 500 ns,'1'
    > > after 550 ns,'0' after 600 ns;

    >
    > You could simplify this, e.g. for a test bench for the 1-wire protocol of
    > http://www.frank-buss.de/vhdl/spartan3e.html I've used a loop:
    >
    > constant rom_test: unsigned(63 downto 0) := x"cf000000e4ec2933";
    > ...
    > test_loop: process
    > variable rom: unsigned(63 downto 0);
    > begin
    > ...
    > -- simulate ROM result
    > rom := rom_test;
    > for j in 1 to 64 loop
    > wait until ds_wire = '0';
    > wait until ds_wire = 'Z';
    > if rom(0) = '0' then
    > ds_wire <= '0';
    > wait for 30 us;
    > ds_wire <= 'Z';
    > wait for 1 us;
    > end if;
    > rom := shift_right(rom, 1);
    > end loop;
    > ...
    >
    > > What I don't understand now is how do I display the contents of the
    > > signals current_kbclk and current_data which are internal to the entity
    > > code_test_process1 so that I may check if the inputs are sampled only
    > > at sys_clk or not. How do I display those signals as well on the wave?

    >
    > This depends on the program you are using. With ActiveHDL you simply
    > drag-and-drop all signals to the wave form window, including internal
    > signals from sub entities.
    >
    > --
    > Frank Buss,
    > http://www.frank-buss.de, http://www.it4-systems.de
     
    , Sep 2, 2006
    #3
  4. Frank Buss Guest

    wrote:

    > Now I seem to have a different problem. In
    > my test_bench entity(i.e. in the architecture part) I have made sys_clk
    > work like a clock for a specified period of time. It isn't showing up
    > on the wave window when I simulate for about 600 ns.


    Again, the solution depends on the software you are using. In ActiveHDL I
    can define a clock stimuli in the wave window for every signal. With ISE
    WebPack I didn't found a way how to add a stimuli. But my test bench, and
    maybe yours, works in both programs with this additional process:

    update_clock: process
    begin
    while true loop
    clk <= not clk;
    wait for 10 ns;
    end loop;
    end process;

    --
    Frank Buss,
    http://www.frank-buss.de, http://www.it4-systems.de
     
    Frank Buss, Sep 2, 2006
    #4
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