divide by 3

Discussion in 'VHDL' started by hsvjap, Sep 12, 2008.

  1. hsvjap

    hsvjap

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    hi all,

    how do u design a divide by 3 ckt (seq ckt) with 50% duty cycle ?

    thnx in advance
     
    hsvjap, Sep 12, 2008
    #1
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