Divide by n

Discussion in 'VHDL' started by Mushmech, Apr 11, 2004.

  1. Mushmech

    Mushmech Guest

    Trying to come up with a simple divide by 16 counter. Please Help!
    Mushmech, Apr 11, 2004
    #1
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  2. constant DIVIDER: integer:= 16;
    signal OVERFLOW: boolean;
    singnal CNT, CNT_NEXT: integer range 0 to DIVIDER - 1;

    OVERFLOW <= (CNT = DIVIDER - 1);

    process(CNT: integer)
    begin
    if OVERFLOW then
    CNT_NEXT <= CNT + 1;
    else
    CNT_NEXT <= 0;
    end if;
    end process;

    process (CLK, RST)
    begin
    if RST = '1' then
    CNT <= 0;
    else if CLK = '1' and CLK'event then
    CNT <= CNT_NEXT;
    end if;
    end process;
    valentin tihomirov, Apr 11, 2004
    #2
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  3. "Mushmech" <> wrote in message news:<IM2ec.57861$z%-kc.rr.com>...
    > Trying to come up with a simple divide by 16 counter. Please Help!


    This is a variation on the divider in the VHDL FAQ; if the modulus is
    even, the output clock is symmetrical, otherwise the high and low
    clock output times differ by 1 clock period:

    --------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    --------------------------------------------------------------------------------
    entity clock_divider is
    generic(modulus: in positive range 2 to integer'high);
    port( clk_in : in std_logic;
    enable : in std_logic := '1';
    reset : in std_logic := '0';
    clk_out : out std_logic );
    end clock_divider;

    architecture behavior of clock_divider is
    begin
    process (clk_in, reset, enable )

    variable count: natural range 0 to modulus - 1;

    begin
    if reset = '1' then
    count := 0;
    clk_out <= '0';
    elsif rising_edge( clk_in ) then
    if enable = '1' then
    if count = modulus - 1 then
    count := 0;
    else
    count := count + 1;
    end if; --count = modulus - 1
    else
    count := count;
    end if; --enable = '1'
    if count >= modulus/2 then
    clk_out <= '0';
    else
    clk_out <= '1';
    end if; --count >= modulus/2
    end if; --rising_edge( clk_in )
    end process;
    end behavior;


    Charles
    Charles M. Elias, Apr 12, 2004
    #3
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