divide by zero error from XILINX ISE

Discussion in 'VHDL' started by Amish Rughoonundon, Jun 10, 2011.

  1. Hi,
    I have this code. XILINX ISE Is giving me an error HDLParsers:866
    "Division by zero" during synthesis. Why is that? Thanks for the help

    Code:
    CONSTANT CLOCK_FREQUENCY        : integer := 50000000;      -- Input
    clock frequency in hertz
    
    CONSTANT SWITCHING_FREQUENCY    : integer := 400000;        -- date
    drive frequency in hertz
    
    CONSTANT CLOCK_END_RAMP_RESET_A             : integer :=
    INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/
    REAL(CLOCK_FREQUENCY)))-1;
    
     
    Amish Rughoonundon, Jun 10, 2011
    #1
    1. Advertising

  2. Amish Rughoonundon wrote:

    > Hi,
    > I have this code. XILINX ISE Is giving me an error HDLParsers:866
    > "Division by zero" during synthesis. Why is that? Thanks for the help
    >
    >
    Code:
    > CONSTANT CLOCK_FREQUENCY        : integer := 50000000;      -- Input
    > clock frequency in hertz
    >
    > CONSTANT SWITCHING_FREQUENCY    : integer := 400000;        -- date
    > drive frequency in hertz
    >
    > CONSTANT CLOCK_END_RAMP_RESET_A             : integer :=
    > INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/
    > REAL(CLOCK_FREQUENCY)))-1;
    > 


    I have no idea. One thing I do know: your code looks overcomplicated (to
    me).

    If I'm not mistaken, the above is identical to:

    constant CLOCK_END_RAMP_RESET_A : integer :=
    integer(0.5 * real(CLOCK_FREQUENCY) / real(SWITCHING_FREQUENCY)) - 1;

    For the rest: I don't have real experience with Xilinx (or any other
    synthesizer for that matter).

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
     
    Paul Uiterlinden, Jun 10, 2011
    #2
    1. Advertising

  3. Amish Rughoonundon

    Gabor Sz Guest

    On Jun 10, 11:53 am, Amish Rughoonundon <>
    wrote:
    > Hi,
    >  I have this code. XILINX ISE Is giving me an error HDLParsers:866
    > "Division by zero" during synthesis. Why is that? Thanks for the help
    >
    >
    Code:
    > CONSTANT CLOCK_FREQUENCY        : integer := 50000000;      -- Input
    > clock frequency in hertz
    >
    > CONSTANT SWITCHING_FREQUENCY    : integer := 400000;        -- date
    > drive frequency in hertz
    >
    > CONSTANT CLOCK_END_RAMP_RESET_A             : integer :=
    > INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/
    > REAL(CLOCK_FREQUENCY)))-1;
    > 


    I'm going to take a wild guess that Xilinx is taking 1/CLOCK_FREQUENCY
    and converting it to integer zero, instead of using a real for the
    final
    divide operation. Perhaps using Paul's simplified version will fix
    the problem. The other possibility is that Xilinx's real format has
    an underflow for 1/50000000. This might happen if they don't use
    enough bits when dividing the mantissas for the intermediate result.
    Either way it could be called a bug. IEEE floating point has defined
    the temporary precision just for this sort of issue.

    -- Gabor
     
    Gabor Sz, Jun 11, 2011
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Sachin
    Replies:
    1
    Views:
    681
  2. nfirtaps
    Replies:
    1
    Views:
    1,417
    Mike Treseler
    Aug 31, 2006
  3. shuisheng

    Divide by zero.

    shuisheng, Sep 25, 2006, in forum: C++
    Replies:
    4
    Views:
    413
    Victor Bazarov
    Sep 25, 2006
  4. revu
    Replies:
    5
    Views:
    2,303
  5. Replies:
    3
    Views:
    1,194
    Mike Treseler
    May 8, 2008
Loading...

Share This Page