A
Amish Rughoonundon
Hi,
I have this code. XILINX ISE Is giving me an error HDLParsers:866
"Division by zero" during synthesis. Why is that? Thanks for the help
I have this code. XILINX ISE Is giving me an error HDLParsers:866
"Division by zero" during synthesis. Why is that? Thanks for the help
Code:
CONSTANT CLOCK_FREQUENCY : integer := 50000000; -- Input
clock frequency in hertz
CONSTANT SWITCHING_FREQUENCY : integer := 400000; -- date
drive frequency in hertz
CONSTANT CLOCK_END_RAMP_RESET_A : integer :=
INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/
REAL(CLOCK_FREQUENCY)))-1;