Do I have a race condition for clk33_div?

Discussion in 'VHDL' started by Tim Doyle, Jun 12, 2009.

  1. Tim Doyle

    Tim Doyle Guest

    I am looking to determine if the following VHDL process block creates
    a race condition for clk33_div, given that it is a signal that is
    being updated seemingly at same time it is being evaluated if I
    understand VHDL constructs.

    Any thoughts or guidelines would be greatly appreciated.

    Regards,

    Tim Doyle

    Here is the code:


    CLOCK_DIV: process (clk33, resetn)
    begin
    if resetn = '0' then
    clk33_div <= (others =>'0');
    clock_out <= '0';
    elsif clk33'event and clk33 = '1' then
    if clk33_div = "11000" then
    clk33_div <= (others => '0');
    clock_out <= not(clock_out);
    else
    clk33_div <= clk33_div + '1';
    clock_out <= clock_out;
    end if;
    end if;
    end process;
     
    Tim Doyle, Jun 12, 2009
    #1
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  2. Tim Doyle

    Barry Guest

    On Jun 12, 8:29 am, Tim Doyle <> wrote:
    > I am looking to determine if the following VHDL process block creates
    > a race condition for clk33_div, given that it is a signal that is
    > being updated seemingly at same time it is being evaluated if I
    > understand VHDL constructs.
    >
    > Any thoughts or guidelines would be greatly appreciated.
    >
    > Regards,
    >
    > Tim Doyle
    >
    > Here is the code:
    >
    > CLOCK_DIV: process (clk33, resetn)
    >         begin
    >                 if resetn = '0' then
    >                         clk33_div <= (others =>'0');
    >                         clock_out <= '0';
    >                 elsif clk33'event and clk33 = '1' then
    >                         if clk33_div = "11000" then
    >                                 clk33_div <= (others => '0');
    >                                 clock_out <= not(clock_out);
    >                         else
    >                                 clk33_div <= clk33_div + '1';
    >                                 clock_out <= clock_out;
    >                         end if;
    >                 end if;
    >         end process;


    Hi Tim,

    In VHDL, a signal is not assigned its new value until you reach the
    "end process" statement (or a wait statement). This is different from
    the behavior of a variable in a process.

    Barry
     
    Barry, Jun 12, 2009
    #2
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  3. > On Jun 12, 8:29 am, Tim Doyle <> wrote:
    >> I am looking to determine if the following VHDL process block creates
    >> a race condition for clk33_div, given that it is a signal that is
    >> being updated seemingly at same time it is being evaluated


    As long as I use clk33 as the only clock and
    clk_div as an enable input for other logic
    on the same clock, there will be no timing problems.
    Think of the right side of an assignment as
    gates on the D side of the flop

    Barry wrote:
    > In VHDL, a signal is not assigned its new value until you reach the
    > "end process" statement


    Which happens once every clock tick in Tim's example.
    The code looks functional to me.
    clock_out <= clock_out; is not necessary.

    -- Mike Treseler
     
    Mike Treseler, Jun 12, 2009
    #3
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