Does VHDL support standard probability distributions

Discussion in 'VHDL' started by Daku, Dec 14, 2009.

  1. Daku

    Daku Guest

    Could some VHDL guru please help ? I am trying to generate a jittery
    clock pulse e.g., clock pulses with pulse width jitter distributed in
    an uniform distribution, within pre-defined upper and lower bounds,
    e.g., something similar to $dist_uniform in Verilog. Any hints
    suggestions would be of immense help.
    Thank you.
     
    Daku, Dec 14, 2009
    #1
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  2. Jonathan Bromley <> writes:

    > Don't touch the seed variables - just prime them with some
    > value,


    Clearly one of the them should be initialised to '42', but what about
    the other one :)

    Cheers,
    Martin

    --

    TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    http://www.conekt.net/electronics.html
     
    Martin Thompson, Dec 14, 2009
    #2
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