Don't worriy assignment, when to worry about?

[Valentin Tihomirov]

for example

--wait on clk_edage;
if cleaning = '1' then
data <= in; -- no need to keep data
end if;

Register keeps data while cleaning = '0' (cleaing variable here = NextEmpty
signal). When cleaning signal becomes active we can load the register with
fresh data. In fact, I have to assign inputs to the data only when loading
of the register is requested. That is, the following describes the logic
more precisely allowing for more degree of freedom to compiler (as well as
P&R?).

--wait on clk_edage;
if cleaning = '1' then -- becomes empty, can be loaded
if loading = '1' then -- load request
data <= in;
else
data <= 'X';
end if;
end if;

On the other hand, the latter can be much harder to read assuming that logic
can have more than two binary decision conditions (and hense much more
complex branching).