doubt about packages in vhdl

[chaitanyakurmala]

hi all,
i am a beginner in vhdl and i am using xilinx 8.1 and modelsim xe6.0
for my purpose and i am having a doubt on the packages.
i.e.,
let me say i want to write a program on some adder and for that purpose
i have declared a package (say) called adderpackage.
so in my adder program i will use declaration like this

use work.adderpackage.all;

my question is that when xilinx is started and new project is
created.we will have only project name and device name in sources
window and then we have to select device and by right click add new
source i will add my program of adder. so where my package file to be
added and will the program simulates with out addition of package file
in present project.

plz help me in this regard.thanks for help in advance

 

[J.Ram]

Hi,
Tou can add package file(say adderpackage.vhd), in xilinx by right
click on device and add source file and then use GUI to select your
package file and that will be seen in your source.
regards
J.Ram

 

[chaitanyakurmala]

dear ram add source or add new source
let me say i right click device and add new source and in that i
selected VHDL package.and defined the package and saved. again right
click the device and add new source and selected vhdlmodule and written
my design ( in this i called that package defined previously as use
work.adderpackage.all)will it show any error at any point of design
flow. and one more thing do i have to verify the functionality of
package or just syntax checking is enough)

 

[J.Ram]

Hi,
right click on device and use add source for existing vhdl file, and
new source for new file
tet written.
for package syntex chech is enough in my knowledge.
Regards
J.Ram