doubt in FLI Program and order of execution

Discussion in 'VHDL' started by priya, Oct 3, 2005.

  1. priya

    priya Guest

    Hi all,

    I have written simple 2-input and gate vhdl code.I am passing
    2-input from FLI to VHDL Code and also sending VHDL Andgate output to
    FLI.I am using modelsim to executed my code

    Here i am pasting both VHDL and FLI CODE.



    VHDL CODE:


    entity and4 is
    port ( in1, in2 : in bit;
    out1 : out bit
    );
    end;
    architecture only of and4 is
    attribute foreign : string;
    attribute foreign of only :architecture is "and_gate_init ./gates.dll";


    begin
    out1<=in1 and in2;
    end;


    -----------------------------------------
    entity and_output is
    port ( out1: in bit;
    out2 : out bit
    );
    end;
    architecture out_arch of and_output is
    attribute foreign : string;
    attribute foreign of out_arch :architecture is "and_gate_init_output
    ../gates.dll";

    begin
    end;


    -- -- -- -----------------------
    entity testbench is
    end testbench;
    architecture and_arch of testbench is
    component and4
    port ( in1, in2 : in bit;
    out1 : out bit
    );
    end component;
    component and_output
    port ( out1: in bit;
    out2: out bit
    );
    end component;

    signal in1 : bit;
    signal in2 : bit;
    signal out1 : bit;
    signal out2 : bit;
    begin
    t1 : and4 port map ( in1, in2, out1 );
    t2 : and_output port map ( out1,out2);
    end and_arch ;




    VHDL-FLI CODE


    #include <stdio.h>
    #include "mti.h"

    typedef struct {
    mtiSignalIdT in1;
    mtiSignalIdT in2;
    mtiSignalIdT out1;
    mtiSignalIdT out2;
    } inst_rec;





    void do_and( void * param )
    {
    inst_rec * ip = (inst_rec *)param;
    mtiInt32T val1, val2,val3;
    mtiInt32T result;

    mti_SetSignalValue( ip->in1,1);
    mti_SetSignalValue( ip->in2,1);

    }



    void and_gate_init(

    mtiRegionIdT region,
    char *param,
    mtiInterfaceListT *generics,
    mtiInterfaceListT *ports
    )
    {
    inst_rec *ip;
    mtiSignalIdT outp;
    mtiProcessIdT proc;

    mti_PrintFormatted("hello FLI Code\n");

    ip = (inst_rec *)mti_Malloc( sizeof(inst_rec) );
    ip->in1 = mti_FindPort( ports, "in1" );
    ip->in2 = mti_FindPort( ports, "in2" );

    proc = mti_CreateProcess( "p1", do_and, ip );

    }

    void do_and1( void * param )
    {
    inst_rec * ip = (inst_rec *)param;
    mtiInt32T val1, val2;
    mtiInt32T result;

    val1 = mti_GetSignalValue( ip->out1 );


    mti_PrintFormatted("variable values out1 is %d\n",val1);


    }

    void and_gate_init_output(
    mtiRegionIdT region,
    char *param,
    mtiInterfaceListT *generics,
    mtiInterfaceListT *ports
    )
    {
    inst_rec *ip;
    mtiSignalIdT outp;
    mtiProcessIdT proc;

    ip = (inst_rec *)mti_Malloc( sizeof(inst_rec) );

    ip->out2= mti_FindPort( ports, "out2" );
    ip->out1= mti_FindPort( ports, "out1" );

    proc = mti_CreateProcess( "p1", do_and1, ip );

    }



    question No :1



    t1 : and4 port map ( in1, in2, out1 );

    This module instantions is used to get the 2-input value from fli code
    by calling foreign attribute.

    Here I am able to get the 2-input.But I have one doubt.

    here
    void and_gate_init( ---this method is in FLI CODE.


    attribute foreign of only :architecture is "and_gate_init ./gates.dll";
    ---this line is in VHDL CODe...

    Here i am calling and_gate_init foreign method only one times.but
    here the and_gate_init method will be executed two times.

    for ex I added printf statement in and_gate_init method...

    I got the following output


    hello FLI Code
    hello FLI Code

    it printed 2 times...
    I dont know the how they method called two times.


    question No.2: output foreign attribute also called two times...



    2.


    begin
    t1 : and4 port map ( in1, in2, out1 );
    t2 : and_output port map ( out1,out2);
    end and_arch ;



    Here I have one more doubt..How these two module instantaions
    executed..It means that it Executed parallely or sequentially?

    As far as my knowleage it executed Parallely....

    but here i want to send the out1 value to input of the second module...

    How it is possible? need to add any delay?


    plz anyone reply my question.if u are not clear my question ,plz let me
    know....I will explain in detail.....


    can we mix structual and data flow statement in single begin and
    module?



    rdgs
    priya
     
    priya, Oct 3, 2005
    #1
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