doubt in process statement of vhdl

Discussion in 'VHDL' started by chaitanyakurmala@gmail.com, Sep 21, 2006.

  1. Guest

    dear all
    i am constructing a FIFO which is in between 2 clock domains.
    1st domain --clk1
    2nd domain--clk2
    so in my program i written
    process(clk1, clk2)
    {





    }
    so first let me say clk1 triggered process and the code inside the
    process is in the process of execution and in the middle of execution
    if clk2 triggered the process what will happen.will the start
    responding to clk2 trigger instantaneously by suspending the clk1
    trigger or after completing the task of clk1.
    i think i am clear..if not plz tell me for further clarity.the process
    is as follows
    behavior: process (clk_in, clk_out)

    variable fifo_index : natural := 0;
    variable i : natural ;
    variable fifo_buffer : buffer_type;
    variable req_temp : std_logic := '0';

    begin
    --n := fifo_index;
    -- Accept input
    if clk_in'event and clk_in = '1' then
    if chan_in.req = '1' and fifo_index < buffer_size then
    fifo_index := fifo_index + 1;
    index_delayed <= fifo_index after fifo_delay;
    fifo_buffer(fifo_index) := chan_in;
    end if;
    end if;

    -- Acknowlege input
    if clk_in'event and clk_in = '0' then
    if chan_in.req = '0' then
    ack_in <= '0' after 0.5 ns;
    elsif fifo_index < buffer_size then
    ack_in <= '1' after 0.5 ns;
    end if;
    end if;

    -- Check for output acknowlegements Send output data
    if clk_out'event and clk_out = '1' then
    if ack_out = '1' then
    req_temp := '0';
    if fifo_index > 1 then
    fifo_index := fifo_index - 1;
    end if;
    index_delayed <= fifo_index;

    -- for index in 1 to fifo_index loop
    -- fifo_buffer(index) := fifo_buffer(index + 1);
    --end loop;
    i:=1;
    L1:loop
    fifo_buffer(i) := fifo_buffer(i+1);
    i := i+1;
    if (i = fifo_index+1) then
    exit L1;
    end if;
    end loop L1;
    end if;
    if fifo_index > 0 then
    req_temp := '1';
    chan_out <= fifo_buffer(1) after 0.5 ns;
    end if;
    end if;

    chan_out.req <= req_temp after 0.5 ns;

    end process behavior;

    end Behavioral;
     
    , Sep 21, 2006
    #1
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  2. KJ Guest

    <> wrote in message
    news:...
    > dear all
    > i am constructing a FIFO which is in between 2 clock domains.
    > 1st domain --clk1
    > 2nd domain--clk2
    > so in my program i written
    > process(clk1, clk2)
    > {
    >
    >
    >
    >
    >
    > }
    > so first let me say clk1 triggered process and the code inside the
    > process is in the process of execution and in the middle of execution
    > if clk2 triggered the process what will happen.will the start
    > responding to clk2 trigger instantaneously by suspending the clk1
    > trigger or after completing the task of clk1.
    > i think i am clear..if not plz tell me for further clarity.the process
    > is as follows


    This will not be synthesizable (not sure if that is your intention here or
    if you just want to write a model for a fifo for simulation only purposes).
    If you do intend for this to be synthesizable (i.e. implement it in a
    physical part) you can not have a process triggered by edges of two
    different signals (i.e. clk1, clk2) or by different edges (later in the code
    you looked for rising edges as well as falling edges). If you really need
    all of this you'll need to have four processes: two that are triggered by
    events on clk1 and two more that are triggered by events on clk2 In
    addition you can not use the 'after' clause (i.e. ack_in <= '1' after 0.5
    ns; is not synthesizable). There may be other problems but those are the
    first that jumped out.

    If, on the other hand, if all you're trying to do is make a simulation model
    of a fifo then in regards to your question..

    "if clk2 triggered the process what will happen.will the start responding to
    clk2 trigger instantaneously by suspending the clk1 trigger or after
    completing the task of clk1."

    the answer is that a process will always run to completion or until it
    voluntarily gives up control (via a 'wait' statement). If 'clk2' triggered
    the process then this implies that the clk1 task had already completed so
    there is no chance of the clk1 proces being suspended as a result of
    anything to do with clk2.

    KJ
     
    KJ, Sep 21, 2006
    #2
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  3. Andy Guest

    Some synthesis tools allow multiple clocks/edges in one process, so
    long as the same signal/variable is not assigned on more than one
    clock/edge. Synplify is one such synthesis tool, and I believe Quartus
    is as well.

    Andy


    KJ wrote:
    > <> wrote in message
    > news:...
    > > dear all
    > > i am constructing a FIFO which is in between 2 clock domains.
    > > 1st domain --clk1
    > > 2nd domain--clk2
    > > so in my program i written
    > > process(clk1, clk2)
    > > {
    > >
    > >
    > >
    > >
    > >
    > > }
    > > so first let me say clk1 triggered process and the code inside the
    > > process is in the process of execution and in the middle of execution
    > > if clk2 triggered the process what will happen.will the start
    > > responding to clk2 trigger instantaneously by suspending the clk1
    > > trigger or after completing the task of clk1.
    > > i think i am clear..if not plz tell me for further clarity.the process
    > > is as follows

    >
    > This will not be synthesizable (not sure if that is your intention here or
    > if you just want to write a model for a fifo for simulation only purposes).
    > If you do intend for this to be synthesizable (i.e. implement it in a
    > physical part) you can not have a process triggered by edges of two
    > different signals (i.e. clk1, clk2) or by different edges (later in the code
    > you looked for rising edges as well as falling edges). If you really need
    > all of this you'll need to have four processes: two that are triggered by
    > events on clk1 and two more that are triggered by events on clk2 In
    > addition you can not use the 'after' clause (i.e. ack_in <= '1' after 0.5
    > ns; is not synthesizable). There may be other problems but those are the
    > first that jumped out.
    >
    > If, on the other hand, if all you're trying to do is make a simulation model
    > of a fifo then in regards to your question..
    >
    > "if clk2 triggered the process what will happen.will the start responding to
    > clk2 trigger instantaneously by suspending the clk1 trigger or after
    > completing the task of clk1."
    >
    > the answer is that a process will always run to completion or until it
    > voluntarily gives up control (via a 'wait' statement). If 'clk2' triggered
    > the process then this implies that the clk1 task had already completed so
    > there is no chance of the clk1 proces being suspended as a result of
    > anything to do with clk2.
    >
    > KJ
     
    Andy, Sep 21, 2006
    #3
  4. Processes are only a way to describe sequential logic, so it can even be
    done everything in the same process but the major problem is that each
    signal will turn out as a flip flop, a hardware coded object, which will
    not be able to be clocked on both rising and falling edge of the clock.
    Think to the hardware before writing the code is the best way to
    understand vhdl in my opinion.
    regards

    Alessandro

    Andy wrote:
    > Some synthesis tools allow multiple clocks/edges in one process, so
    > long as the same signal/variable is not assigned on more than one
    > clock/edge. Synplify is one such synthesis tool, and I believe Quartus
    > is as well.
    >
    > Andy
    >
    >
    > KJ wrote:
    >
    >><> wrote in message
    >>news:...
    >>
    >>>dear all
    >>>i am constructing a FIFO which is in between 2 clock domains.
    >>>1st domain --clk1
    >>>2nd domain--clk2
    >>>so in my program i written
    >>>process(clk1, clk2)
    >>>{
    >>>
    >>>
    >>>
    >>>
    >>>
    >>>}
    >>>so first let me say clk1 triggered process and the code inside the
    >>>process is in the process of execution and in the middle of execution
    >>>if clk2 triggered the process what will happen.will the start
    >>>responding to clk2 trigger instantaneously by suspending the clk1
    >>>trigger or after completing the task of clk1.
    >>>i think i am clear..if not plz tell me for further clarity.the process
    >>>is as follows

    >>
    >>This will not be synthesizable (not sure if that is your intention here or
    >>if you just want to write a model for a fifo for simulation only purposes).
    >>If you do intend for this to be synthesizable (i.e. implement it in a
    >>physical part) you can not have a process triggered by edges of two
    >>different signals (i.e. clk1, clk2) or by different edges (later in the code
    >>you looked for rising edges as well as falling edges). If you really need
    >>all of this you'll need to have four processes: two that are triggered by
    >>events on clk1 and two more that are triggered by events on clk2 In
    >>addition you can not use the 'after' clause (i.e. ack_in <= '1' after 0.5
    >>ns; is not synthesizable). There may be other problems but those are the
    >>first that jumped out.
    >>
    >>If, on the other hand, if all you're trying to do is make a simulation model
    >>of a fifo then in regards to your question..
    >>
    >>"if clk2 triggered the process what will happen.will the start responding to
    >>clk2 trigger instantaneously by suspending the clk1 trigger or after
    >>completing the task of clk1."
    >>
    >>the answer is that a process will always run to completion or until it
    >>voluntarily gives up control (via a 'wait' statement). If 'clk2' triggered
    >>the process then this implies that the clk1 task had already completed so
    >>there is no chance of the clk1 proces being suspended as a result of
    >>anything to do with clk2.
    >>
    >>KJ

    >
    >
     
    alessandro basili, Sep 22, 2006
    #4
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