doubt in this program plz tell why this error is coming and what modifications i have to do

Discussion in 'VHDL' started by chaitanyakurmala@gmail.com, Sep 21, 2006.

  1. Guest

    this is a program for asynchronous FIFO such that it is operating in
    between two clock domains transfering 8bit parallel data from one
    domain to another.
    there are 16 fifo buffers in between the two clock modules.the code is
    written such that it is shifting the data and transfering always the
    data in buffer1 to clockmodule 2.
    the error coming is
    Xst:787 - "D:/ise projects/fifo12/fifo1p.vhd" line 94: Index value <17>
    is not in Range of array <fifo_buffer>.
    i indicated the line in which error is coming in inverted columns and
    also put stars between start and end of line
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use work.bus_package.all;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity fifo1p is
    Port ( chan_in : in channel;
    chan_out : out channel := init_chan_values;
    ack_in : out STD_LOGIC;
    ack_out : in STD_LOGIC := '0';
    clk_in : in STD_LOGIC;
    clk_out : in STD_LOGIC);
    end fifo1p;

    architecture Behavioral of fifo1p is

    -- FIFO delay is that portion of delay not due to clock mismatch
    constant fifo_delay : time := 1.5 ns;
    constant buffer_size : natural := 16;

    type buffer_type is array (1 to buffer_size) of channel;

    signal index_delayed : natural := 0;
    --constant i:natural :=1;

    begin

    behavior: process (clk_in, clk_out)

    variable fifo_index : natural := 0;
    variable i : natural ;
    variable fifo_buffer : buffer_type;
    variable req_temp : std_logic := '0';

    begin
    --n := fifo_index;
    -- Accept input
    if clk_in'event and clk_in = '1' then
    if chan_in.req = '1' and fifo_index < buffer_size then
    fifo_index := fifo_index + 1;
    index_delayed <= fifo_index after fifo_delay;
    fifo_buffer(fifo_index) := chan_in;
    end if;
    end if;

    -- Acknowlege input
    if clk_in'event and clk_in = '0' then
    if chan_in.req = '0' then
    ack_in <= '0' after 0.5 ns;
    elsif fifo_index < buffer_size then
    ack_in <= '1' after 0.5 ns;
    end if;
    end if;

    -- Check for output acknowlegements Send output data
    if clk_out'event and clk_out = '1' then
    if ack_out = '1' then
    req_temp := '0';
    if fifo_index > 1 then
    fifo_index := fifo_index - 1;
    end if;
    index_delayed <= fifo_index;

    -- for index in 1 to fifo_index loop
    -- fifo_buffer(index) := fifo_buffer(index + 1);
    --end loop;
    i:=1;
    L1:loop
    *****"fifo_buffer(i) := fifo_buffer(i+1);"******
    i := i+1;
    if (i = fifo_index+1) then
    exit L1;
    end if;
    end loop L1;
    end if;
    if fifo_index > 0 then
    req_temp := '1';
    chan_out <= fifo_buffer(1) after 0.5 ns;
    end if;
    end if;

    chan_out.req <= req_temp after 0.5 ns;

    end process behavior;

    end Behavioral;
     
    , Sep 21, 2006
    #1
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  2. Re: doubt in this program plz tell why this error is coming and whatmodifications i have to do

    When fifo_index is 15 it will still be incremented by one, because on
    the chan_in.req = '1' the condition is true, so it will go to 16. It
    means that fifo_index + 1 = 17, means that last time you addressed
    fifo_buffer you will have fifo_buffer (16) := fifo_buffer (17), over the
    constrained declaration.
    Why don't you just use fifo_index as the index, without this i loop?

    wrote:
    > this is a program for asynchronous FIFO such that it is operating in
    > between two clock domains transfering 8bit parallel data from one
    > domain to another.
    > there are 16 fifo buffers in between the two clock modules.the code is
    > written such that it is shifting the data and transfering always the
    > data in buffer1 to clockmodule 2.
    > the error coming is
    > Xst:787 - "D:/ise projects/fifo12/fifo1p.vhd" line 94: Index value <17>
    > is not in Range of array <fifo_buffer>.
    > i indicated the line in which error is coming in inverted columns and
    > also put stars between start and end of line
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    > use work.bus_package.all;
    >
    > ---- Uncomment the following library declaration if instantiating
    > ---- any Xilinx primitives in this code.
    > --library UNISIM;
    > --use UNISIM.VComponents.all;
    >
    > entity fifo1p is
    > Port ( chan_in : in channel;
    > chan_out : out channel := init_chan_values;
    > ack_in : out STD_LOGIC;
    > ack_out : in STD_LOGIC := '0';
    > clk_in : in STD_LOGIC;
    > clk_out : in STD_LOGIC);
    > end fifo1p;
    >
    > architecture Behavioral of fifo1p is
    >
    > -- FIFO delay is that portion of delay not due to clock mismatch
    > constant fifo_delay : time := 1.5 ns;
    > constant buffer_size : natural := 16;
    >
    > type buffer_type is array (1 to buffer_size) of channel;
    >
    > signal index_delayed : natural := 0;
    > --constant i:natural :=1;
    >
    > begin
    >
    > behavior: process (clk_in, clk_out)
    >
    > variable fifo_index : natural := 0;
    > variable i : natural ;
    > variable fifo_buffer : buffer_type;
    > variable req_temp : std_logic := '0';
    >
    > begin
    > --n := fifo_index;
    > -- Accept input
    > if clk_in'event and clk_in = '1' then
    > if chan_in.req = '1' and fifo_index < buffer_size then
    > fifo_index := fifo_index + 1;
    > index_delayed <= fifo_index after fifo_delay;
    > fifo_buffer(fifo_index) := chan_in;
    > end if;
    > end if;
    >
    > -- Acknowlege input
    > if clk_in'event and clk_in = '0' then
    > if chan_in.req = '0' then
    > ack_in <= '0' after 0.5 ns;
    > elsif fifo_index < buffer_size then
    > ack_in <= '1' after 0.5 ns;
    > end if;
    > end if;
    >
    > -- Check for output acknowlegements Send output data
    > if clk_out'event and clk_out = '1' then
    > if ack_out = '1' then
    > req_temp := '0';
    > if fifo_index > 1 then
    > fifo_index := fifo_index - 1;
    > end if;
    > index_delayed <= fifo_index;
    >
    > -- for index in 1 to fifo_index loop
    > -- fifo_buffer(index) := fifo_buffer(index + 1);
    > --end loop;
    > i:=1;
    > L1:loop
    > *****"fifo_buffer(i) := fifo_buffer(i+1);"******
    > i := i+1;
    > if (i = fifo_index+1) then
    > exit L1;
    > end if;
    > end loop L1;
    > end if;
    > if fifo_index > 0 then
    > req_temp := '1';
    > chan_out <= fifo_buffer(1) after 0.5 ns;
    > end if;
    > end if;
    >
    > chan_out.req <= req_temp after 0.5 ns;
    >
    > end process behavior;
    >
    > end Behavioral;
    >
     
    alessandro basili, Sep 21, 2006
    #2
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