doubt in variable passing in multiple process

[chaitanyakurmala]

let me say

i am having two processes
process(clk1) and process(clk2)


process(clk1)
variable x:natural:=0;
begin
if clk'event and clk='1' then
x := x+1;
end if
end process;

process(clk2)
begin
----
-------
-----
end process

in the 1st process x may be changed to some 10 let me say.
and i want that variable with changed value to be utilized in 2nd
process how can i do it.
if i declare variable x before process1 it is giving error that shared
variables only should be declared here.
thank you

 

[David Ashley]

let me say

i am having two processes
process(clk1) and process(clk2)


process(clk1)
variable x:natural:=0;
begin
if clk'event and clk='1' then
x := x+1;
end if
end process;

process(clk2)
begin
----
-------
-----
end process

in the 1st process x may be changed to some 10 let me say.
and i want that variable with changed value to be utilized in 2nd
process how can i do it.
if i declare variable x before process1 it is giving error that shared
variables only should be declared here.
thank you

Dude there's gotta be a better way of learning the language. This
is too much hand holding, these are fundamental things in VHDL.
Read your book, work the examples. It's all there...

-Dave

 

[alessandro basili]

Variable declared in a process are only available for that process. I
think you better study some more basics before approaching any project.

 

[Paul Uiterlinden]

let me say

i am having two processes
process(clk1) and process(clk2)


process(clk1)
variable x:natural:=0;
begin
if clk'event and clk='1' then
x := x+1;
end if
end process;

process(clk2)
begin
----
-------
-----
end process

in the 1st process x may be changed to some 10 let me say.
and i want that variable with changed value to be utilized in 2nd
process how can i do it.

Use a signal. Signals are the normal way for communication between
processes.

if i declare variable x before process1 it is giving error that
shared variables only should be declared here.
thank you

Variables declared outside a process must be declared shared. But stay
away from shared variables as a beginner. With shared variables it is
possible to create non-deterministic behavior. So for now stay clear.
First learn the fundamentals of VHDL.

 

[Mike Treseler]

Use a signal. Signals are the normal way for communication between
processes.

Or do all of the logic using the variable x_v in the same process.
A process port assignment like
my_port <= x_v;
will then do the job without any interposed signals.

-- Mike Treseler