doubt in vhdl program and fpga ( key bebouncing)

[chaitu]

hai i am a beginner of vhdl plz help

i am suspecting that whether my virtex xcv50 fpga is having key
bebouncing problem and so i decided to test it and execeuted this
program shown below
but even i made 'a' as high in my virtex fpga
i am not getting output changed to 0000000000000001.

as i have given 'a' in process i expect x to change to
0000000000000001 which afterwards is assinged to output.
i expected that if debouncing is there output will be some other than
0000000000000001 and 0000000000000000
but i am getting in output leds always 0000000000000000 even i
triggered 'a' to high.

is there any wrong in my checking.

entity testing is
Port ( a : in STD_LOGIC;
--b : in STD_LOGIC;
--or21 : out STD_LOGIC;
--and21 : out STD_LOGIC;
--nor21 : out STD_LOGIC;
output: out std_logic_vector(15 downto 0));
--output1: out std_logic);
end testing;

architecture Behavioral of testing is
--signal dor21,dand21: std_logic;
begin
process(a)
variable x: std_logic_vector(15 downto 0):= "0000000000000000";
begin
--if a = '1' and a'event then
x := x+1;
--end if;
output <= x;
end process;
end Behavioral;