doubt on VHDL process

[chaitanyakurmala]

dear all
i am having a doubt in vhdl process(....)
if i define
process(clk1,clk2)
{
.......
........
}
if 1st clk1 occured and if it takes 5 sec to complete whole process and
if in 3rd sec clk2 has triggered. will the process stops in the middle
and respond to clk2 or it will continue and respond to clk2 after end
of process invoked by clk1

 

[alessandro basili]

Processes are triggered by any changes in any signal in the sensitivity
list, it just depends on how you write the code. Remember that for
"signals" the value will be updated at the end of the process and not in
the "middle" as for the variables.
I would not use two clocks for the same flip-flop though.

 

[Hubble]

dear all
i am having a doubt in vhdl process(....)
if i define
process(clk1,clk2)
{
......
.......
}
if 1st clk1 occured and if it takes 5 sec to complete whole process and
if in 3rd sec clk2 has triggered. will the process stops in the middle
and respond to clk2 or it will continue and respond to clk2 after end
of process invoked by clk1

This cannot happen. If you have processes with sensitivity list, there
can be no WAIT statements in the process body. This means, that the
completion of a process is *always* in the current simulation delta.
You can define signal assignments which occur in the future (e.g.
OUT<='0' after 500 ms), but that does not stop the process.

So on 1st clk1, the process will be triggered and complete in the first
simulation delta.

A process like yours is equivalent to

process
begin
-- sequential statements, WAIT not allowed
...
-- at the very end
WAIT UNTIL clk1'event OR clk2'event;
end;

Inside the sequential statements you can do *anything* which can be
done with algorithms (e.g. binary search, quicksort). From the
simulators point of view, this takes *no* (simulation) time.

Hubble.