doubt regarding port mapping

Discussion in 'VHDL' started by tulip, Oct 29, 2004.

  1. tulip

    tulip Guest

    My code is

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity mod_exp is
    Port ( T : in std_logic_vector(7 downto 0);
    E : in std_logic_vector(7 downto 0);
    M0 : in std_logic_vector(7 downto 0);
    P,G1,G2 : buffer std_logic_vector(7 downto 0);
    Gout : buffer std_logic_vector(7 downto 0)
    );
    end mod_exp;

    architecture structural of mod_exp is

    component str
    port(A : in std_logic_vector(7 downto 0);
    B : in std_logic_vector(7 downto 0);
    M : in std_logic_vector(7 downto 0);
    R : buffer std_logic_vector(7 downto 0)
    );
    end component;
    signal C,one:std_logic_vector(7 downto 0);
    begin
    C<='00000100'; one<='00000001';
    r0:str port map(C,T,M0,P); --line 1
    r1:str port map(C,one,M0,G1); --line 2
    r2:str port map(G1,G1,M0,Gout); --line 3

    end structural;

    IN THE ABOVE CODE, I GOT THE OUTPUTS P AND G1 IN LINE 1 AND LINE 2. BUT I
    AM NOT GETTING THE OUTPUT Gout IN LINE 3. I AM GETTING 0XXXXXXX AS OUTPUT
    FOR Gout. CAN ANYONE SUGGEST THE SOLUTION.
     
    tulip, Oct 29, 2004
    #1
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  2. tulip

    rickman Guest

    tulip wrote:
    >
    > My code is
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > entity mod_exp is
    > Port ( T : in std_logic_vector(7 downto 0);
    > E : in std_logic_vector(7 downto 0);
    > M0 : in std_logic_vector(7 downto 0);
    > P,G1,G2 : buffer std_logic_vector(7 downto 0);
    > Gout : buffer std_logic_vector(7 downto 0)
    > );
    > end mod_exp;
    >
    > architecture structural of mod_exp is
    >
    > component str
    > port(A : in std_logic_vector(7 downto 0);
    > B : in std_logic_vector(7 downto 0);
    > M : in std_logic_vector(7 downto 0);
    > R : buffer std_logic_vector(7 downto 0)
    > );
    > end component;
    > signal C,one:std_logic_vector(7 downto 0);
    > begin
    > C<='00000100'; one<='00000001';
    > r0:str port map(C,T,M0,P); --line 1
    > r1:str port map(C,one,M0,G1); --line 2
    > r2:str port map(G1,G1,M0,Gout); --line 3
    >
    > end structural;
    >
    > IN THE ABOVE CODE, I GOT THE OUTPUTS P AND G1 IN LINE 1 AND LINE 2. BUT I
    > AM NOT GETTING THE OUTPUT Gout IN LINE 3. I AM GETTING 0XXXXXXX AS OUTPUT
    > FOR Gout. CAN ANYONE SUGGEST THE SOLUTION.


    You don't say what the values of G1 or T are. You also did not provide
    the code for the str module. What does str do?

    While we are at it, I don't see where E is used and I don't see where G2
    is assigned a value.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Oct 29, 2004
    #2
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