DOWNTO versus TO keyword on Component instantiation

Discussion in 'VHDL' started by pierre0102@gmail.com, Nov 18, 2008.

  1. Guest

    Hello,

    Does anyone know about the following error in Modelsim ?

    ** Error: xxx.vhd(2435): (vcom-1012) Slice range direction (to) does
    not match slice prefix dire
    ction (downto).

    The slice range direction on the concerned port are identical on the
    entity and on the component declaration (DOWNTO keyword) but I cant
    use slice range direction (TO) in the assigned signal.
    If I set TO every where is does not work better. The only solution is
    using "downto" everywhere...

    Is it a VHDL restriction ?

    Thanks..
     
    , Nov 18, 2008
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  2. jeppe

    Joined:
    Mar 10, 2008
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    Well be sure that these rules followed:

    Highnumber DOWNTO Lownumber like: 10 DOWNTO 0

    Lownumber TO Highnumber like: 0 TO 10

    Jeppe
     
    jeppe, Nov 18, 2008
    #2
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