drive dm9000 using vhdl

[IcYdRIP]

Here I encounter a general problem.

I connect IET9000(which use dm9000 chip) to a Xilinx fpga board. and
there seems no PLD chip on dm9000 that can be programmed using vhdl. so
how can I deal with dm9000? just using the processor interface?

but if using interface to program it. there are 16-bit data/address
bus(shared). so that means I just need read/write this bus according
to the dm9000 register reading/writing timing and the dm9000 chip will
do things left?

thank you!

 

[IcYdRIP]

anyone can give me any instruction? thanks

I connect iet9000 with a xilinx fpga board.
and how can I operaton on dm9000? I mean, the dm9000 has already been
drived in IET9000 or I have to write a driver in VHDL to drive the
dm9000 chip through the processor interface of dm9000? or I can
directly operate on dm9000 according to the read/write timing through
the processor interface of dm9000?
thanks!

 

[Mike Treseler]

I connect iet9000 with a xilinx fpga board.
and how can I operaton on dm9000? I mean, the dm9000 has already been
drived in IET9000 or I have to write a driver in VHDL
No.

or I can
directly operate on dm9000 according to the read/write timing through
the processor interface of dm9000?

That's it.
http://www.invector.nu/iet9000.asp


--Mike Treseler

 

[IcYdRIP]

thank you, Mike

So, I can direct read/write registers. now here comes another problem.

since iet9000 has a 16-bit address/data bus. if the dm9000 wokrs on
8-bit mode, can I seclect 8 bit of iet9000 as address bus, and another
8 bits as databus?

and if dm9000 works on 16-bit, can I define two port: data port and
address port using the same 16-bit bus of iet9000 in my vhdl entity?

thanks!

 

[Mike Treseler]

thank you, Mike

You are welcome.

since iet9000 has a 16-bit address/data bus. if the dm9000 wokrs on
8-bit mode, can I seclect 8 bit of iet9000 as address bus, and another
8 bits as databus?
and if dm9000 works on 16-bit, can I define two port: data port and
address port using the same 16-bit bus of iet9000 in my vhdl entity?

These are decisions that only
the designer can make.
Read all the data.
Try something and see what happens.

-- Mike Treseler

 

[IcYdRIP]

Thanks
I try first