driving bidirectional std_ulogic_vector

Discussion in 'VHDL' started by deepae, Nov 9, 2006.

  1. deepae

    deepae

    Joined:
    Nov 9, 2006
    Messages:
    1
    Hi,

    I am new to VHDL.
    I am verifiying a DUT which has a inout data signal of type std_ulogic_vector. In the Test bench I have port mapped it to a data_tb
    signal of the same type. But when I try to assign values to the data_tb signal
    I get an error "Nonresolved signal data_tb has multiple sources.

    The signal is declared as a inout during component instantiation.
    I cannot change the type of the signal to std_logic_vector since the DUT is
    using std_ulogic_vector.

    can anyone pls help?
    Thanks,
    Deepa
    deepae, Nov 9, 2006
    #1
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