Driving INOUT ports

Discussion in 'VHDL' started by Mike Nicklas, Feb 23, 2004.

  1. Mike Nicklas

    Mike Nicklas Guest

    Hi everyone

    I'm trying to simulate a design using a testbench tool called HDL
    bencher which is integrated with Xilinx ISE.

    The problem i have is that when i set the value of the INOUT signal in
    my design, the testbench does not appear to assert it as desired and the
    port stays at value zero.

    Has anyone else had any similar problems with HDL bencher and ISE?

    Or does anyone have any recommendations / tips for working with INOUT
    signals in designs?

    Thanks in advance

    Mike Nicklas
     
    Mike Nicklas, Feb 23, 2004
    #1
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