DSP48 in synchronous process or not, what's the difference?

Discussion in 'VHDL' started by Ethan Zheng, Jun 10, 2013.

  1. Ethan Zheng

    Ethan Zheng Guest

    I am so curious about the behavior difference between the following codes.
    Please comment,

    CODE1:
    signal reg_in : signed(17 downto 0);
    signal reg_product : signal(35 downto 0);

    Product_out_pipe_process : PROCESS (clk)
    BEGIN
    IF clk'EVENT AND clk = '1' THEM
    reg_in <= port_in; -- multiplication pipeline in
    reg_product <= reg_in * reg_in; -- pipeline out
    port_out <= reg_product;
    END IF;
    END PROCESS Product_out_pipe_process;

    CODE2:
    signal reg_in : signed(17 downto 0);
    signal reg_product : signal(35 downto 0);
    signal reg_product_1 : signal(35 downto 0);

    Pipe_in_process : PROGRESS (clk)
    BEGIN
    IF clk'EVENT AND clk = '1' THEM
    reg_in <= port_in;
    END IF
    END PROCESS Pipe_in_process;

    reg_product <= reg_in * reg_in; -- multiplication not clk sensitive

    Pipe_out_process : PROGRESS (clk)
    BEGIN
    IF clk'EVENT AND clk = '1' THEM
    reg_product_1 <= reg_product
    END IF
    END PROGRESS Pipe_out_process
    Ethan Zheng, Jun 10, 2013
    #1
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  2. Ethan Zheng

    Andy Guest

    In code2, reg_product is not a register, so it does not consume a clock cycle, but it does consume one in code1.

    Andy
    Andy, Jun 10, 2013
    #2
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  3. Ethan Zheng

    Guest

    Am Montag, 10. Juni 2013 21:08:15 UTC+2 schrieb Ethan Zheng:
    > I am so curious about the behavior difference between the following codes.
    >
    > Please comment,
    >
    >
    >
    > CODE1:
    >
    > signal reg_in : signed(17 downto 0);
    >
    > signal reg_product : signal(35 downto 0);
    >
    >
    >
    > Product_out_pipe_process : PROCESS (clk)
    >
    > BEGIN
    >
    > IF clk'EVENT AND clk = '1' THEM
    >
    > reg_in <= port_in; -- multiplication pipeline in
    >
    > reg_product <= reg_in * reg_in; -- pipeline out
    >
    > port_out <= reg_product;
    >
    > END IF;
    >
    > END PROCESS Product_out_pipe_process;
    >
    >
    >
    > CODE2:
    >
    > signal reg_in : signed(17 downto 0);
    >
    > signal reg_product : signal(35 downto 0);
    >
    > signal reg_product_1 : signal(35 downto 0);
    >
    >
    >
    > Pipe_in_process : PROGRESS (clk)
    >
    > BEGIN
    >
    > IF clk'EVENT AND clk = '1' THEM
    >
    > reg_in <= port_in;
    >
    > END IF
    >
    > END PROCESS Pipe_in_process;
    >
    >
    >
    > reg_product <= reg_in * reg_in; -- multiplication not clk sensitive
    >
    >
    >
    > Pipe_out_process : PROGRESS (clk)
    >
    > BEGIN
    >
    > IF clk'EVENT AND clk = '1' THEM
    >
    > reg_product_1 <= reg_product
    >
    > END IF
    >
    > END PROGRESS Pipe_out_process


    Hi,
    Code1 has a latency of 3 while code 2 has a latency of 2.
    (I assume reg_product1 to be identical with port_out).

    Code 2 could be rewritten like this without functional changes:
    Pipe_out_process : PROGRESS (clk)
    BEGIN
    IF clk'EVENT AND clk = '1' THEM
    reg_product_1 <= reg_in*reg_in; -- now inside sync process,
    END IF
    END PROGRESS Pipe_out_process

    Both architectures might synthesize to DSP48, since the multiplication is enclosed with registers. Additional pipeline stages are possible, but only required if your algorithm needs it. Otherwise you are just wasting clock cycles.

    Have a nice synthesis
    Eilert
    , Jun 12, 2013
    #3
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