Dual Edge

Discussion in 'VHDL' started by R Quijano, Feb 19, 2007.

  1. R Quijano

    R Quijano Guest

    Hi

    You can use my code for a Dual Edge D flipflop which synthetize fine
    with ISE form Xilinx

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity LatchDD is
    Port (D,CLK,R : in STD_LOGIC;
    Q,QN : out STD_LOGIC);
    end LatchDD;

    architecture Behavioral of LatchDD is
    signal Q1,Q2 : std_logic;
    begin
    -- Positive Edge ---
    process(D,clk,R)
    begin
    if R='1' then Q2<='0';
    elsif(rising_edge(clk)) then Q2<=D;
    else null; end if;
    end process;
    -- Negative Edge ---
    process(D,clk,R)
    begin
    if R='1' then Q1<='0';
    elsif(falling_edge(clk)) then Q1<=D;
    else null; end if;
    end process;

    Q <= (Q1 or Q2);
    QN <= not(Q1 or Q2);

    end Behavioral;

    This one checks, both edges. In case you can use the clk'event the
    code will be

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity LatchDD is
    Port (D,CLK,R : in STD_LOGIC;
    Q,QN : out STD_LOGIC);
    end LatchDD;

    architecture Behavioral of LatchDD is
    signal Q1,Q2 : std_logic;
    begin
    -- Positive Edge ---
    process(D,clk,R)
    begin
    if R='1' then Q2<='0';
    elsif(clk'event and clk='1') then Q2<=D;
    else null; end if;
    end process;
    -- Negative Edge ---
    process(D,clk,R)
    begin
    if R='1' then Q1<='0';
    elsif(clk'event and clk='0') then Q1<=D;
    else null; end if;
    end process;

    Q <= (Q1 or Q2);
    QN <= not(Q1 or Q2);

    end Behavioral;


    Have a nice day and hope it help you.
     
    R Quijano, Feb 19, 2007
    #1
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  2. R Quijano schrieb:

    > You can use my code for a Dual Edge D flipflop which synthetize fine
    > with ISE form Xilinx


    ....

    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;


    Don't use these libraries. They are not standard! Furthermore you don't
    need them for this task.


    > entity LatchDD is
    > Port (D,CLK,R : in STD_LOGIC;
    > Q,QN : out STD_LOGIC);
    > end LatchDD;
    >
    > architecture Behavioral of LatchDD is
    > signal Q1,Q2 : std_logic;
    > begin
    > -- Positive Edge ---
    > process(D,clk,R)
    > begin
    > if R='1' then Q2<='0';
    > elsif(rising_edge(clk)) then Q2<=D;
    > else null; end if;
    > end process;
    > -- Negative Edge ---
    > process(D,clk,R)
    > begin
    > if R='1' then Q1<='0';
    > elsif(falling_edge(clk)) then Q1<=D;
    > else null; end if;
    > end process;
    >
    > Q <= (Q1 or Q2);
    > QN <= not(Q1 or Q2);
    >
    > end Behavioral;


    Uhmm ... that is not a dual-edge D-Flipflop.

    If D='1' and the rising_edge(clk) arrives, the output will go '1'. Fine.
    If then D='0' and the falling_edge(clk) arrives, then Q1='0' but the
    output stays at '1' till the next rising_edge(clk). I would expect, that
    the output should fall to '0'.

    If you need a working pseudo dual-edge D-flipflop, have a look at:
    <http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf>.
    The outputs have to be XORed and the flipflops cross-coupled.

    Ralf
     
    Ralf Hildebrandt, Feb 20, 2007
    #2
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  3. R Quijano

    Andy Guest

    On Feb 20, 9:34 am, Ralf Hildebrandt <> wrote:
    > R Quijano schrieb:
    >
    > > You can use my code for a Dual Edge D flipflop which synthetize fine
    > > with ISE form Xilinx

    >
    > ...
    >
    > > use IEEE.STD_LOGIC_ARITH.ALL;
    > > use IEEE.STD_LOGIC_UNSIGNED.ALL;

    >
    > Don't use these libraries. They are not standard! Furthermore you don't
    > need them for this task.
    >
    >
    >
    > > entity LatchDD is
    > > Port (D,CLK,R : in STD_LOGIC;
    > > Q,QN : out STD_LOGIC);
    > > end LatchDD;

    >
    > > architecture Behavioral of LatchDD is
    > > signal Q1,Q2 : std_logic;
    > > begin
    > > -- Positive Edge ---
    > > process(D,clk,R)
    > > begin
    > > if R='1' then Q2<='0';
    > > elsif(rising_edge(clk)) then Q2<=D;
    > > else null; end if;
    > > end process;
    > > -- Negative Edge ---
    > > process(D,clk,R)
    > > begin
    > > if R='1' then Q1<='0';
    > > elsif(falling_edge(clk)) then Q1<=D;
    > > else null; end if;
    > > end process;

    >
    > > Q <= (Q1 or Q2);
    > > QN <= not(Q1 or Q2);

    >
    > > end Behavioral;

    >
    > Uhmm ... that is not a dual-edge D-Flipflop.
    >
    > If D='1' and the rising_edge(clk) arrives, the output will go '1'. Fine.
    > If then D='0' and the falling_edge(clk) arrives, then Q1='0' but the
    > output stays at '1' till the next rising_edge(clk). I would expect, that
    > the output should fall to '0'.
    >
    > If you need a working pseudo dual-edge D-flipflop, have a look at:
    > <http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf>.
    > The outputs have to be XORed and the flipflops cross-coupled.
    >
    > Ralf


    Ralf is correct, you need XOR (or XNOR) encoding and decoding to get
    true dual edge flip flop behavior. These functions have the unique
    feature that any input can control the state of the output, if the
    other inputs are known. It is also expandable to more than two clocks/
    edges (think parity).

    The folowing code is synthesizable in quartus and synplify, but not
    XST (two clock edges), and Precision has/had a bug that does not
    implement one of the registers correctly from the variable.

    process (rst, clk) is
    variable qr, qf : std_logic;
    begin
    if rst = '1' then
    qr := '0';
    qf := '0';
    elsif rising_edge(clk) then
    qr := d xor qf;
    elsif falling_edge(clk) then
    qf := d xor qr;
    end if;
    q <= qr xor qf; -- combo xor of reg'd qr & qf
    end process;

    Andy
     
    Andy, Feb 20, 2007
    #3
  4. Andy schrieb:


    > The folowing code is synthesizable in quartus and synplify, but not
    > XST (two clock edges), and Precision has/had a bug that does not
    > implement one of the registers correctly from the variable.
    >
    > process (rst, clk) is
    > variable qr, qf : std_logic;
    > begin
    > if rst = '1' then
    > qr := '0';
    > qf := '0';
    > elsif rising_edge(clk) then
    > qr := d xor qf;
    > elsif falling_edge(clk) then
    > qf := d xor qr;
    > end if;
    > q <= qr xor qf; -- combo xor of reg'd qr & qf
    > end process;


    Very few synthesis tool support this style. Just have a look at my link
    and code it as it can be seen there in the schematic. The approach of R
    Quijan using 2 processes (one for each edge) will lead you to the right way.

    Ralf
     
    Ralf Hildebrandt, Feb 20, 2007
    #4
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