Dual port Ram - for beginners

Discussion in 'VHDL' started by dwerdna, Apr 3, 2005.

  1. dwerdna

    dwerdna Guest

    Hi all

    Not having thought it was necessary to use a dual port ram until now I
    was after a bit of advice.. I'm getting a few warnings on ModelSim,
    and though I dont think I'm doing anything critically wrong I would
    like to know if it can be improved.

    Im targetting a Spartan 2E, and instantiating ramb4_s8_s8

    I have a sampler which updates a RAM addr every second. My RAM is 64
    addresses deep, therefore storing the previous minutes results which
    the CPU can retrieve and graph at its leisure. I actaully have 8
    different sampler channels, so the RAM is being fully utilised

    I have decided to use a DP RAM as I felt it was a good way for 2
    completely different controllers to access the same information
    independently, which would also reduce my coding lines to make a
    simpler system.

    Both clocks into the RAM are from the same source, so I am getting a
    warning that there is no phase difference between the rising edges of
    the clocks (apparently it needs 0.1ns). Is this something I need to
    modify in some way??

    It is also coming up with a warning that I should not be addressing the
    same address with both ports (currently the ram_enable is hardwired
    '1'), but due to only one side writing and the other side reading I am
    comfortable with this. I will probably implement some arbitration here
    so that I dont get a unknown value for the read if both sides are
    accessing the same address. Again, do I need to worry about this at
    all?? Xilinx does advertise it as 'true dual port ram'.. My read
    sample might be unknown but that is the worst that could happen isnt
    it??

    Thanks for your time

    Andrew
     
    dwerdna, Apr 3, 2005
    #1
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  2. dwerdna wrote:

    > Not having thought it was necessary to use a dual port ram until now I
    > was after a bit of advice.. I'm getting a few warnings on ModelSim,
    > and though I dont think I'm doing anything critically wrong I would
    > like to know if it can be improved.


    Dual port RAM is not really a VHDL - for beginners topic.
    Consider trying a design using registers first.

    > Im targetting a Spartan 2E, and instantiating ramb4_s8_s8
    > I have a sampler which updates a RAM addr every second. My RAM is 64
    > addresses deep, therefore storing the previous minutes results which
    > the CPU can retrieve and graph at its leisure.


    Sounds you could get by with
    one read port and one write port.
    This can be inferred from a vhdl template,
    and requires no arbitration.
    http://groups-beta.google.com/groups?q=vhdl mem_type dual port

    -- Mike Treseler
     
    Mike Treseler, Apr 3, 2005
    #2
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  3. dwerdna

    dwerdna Guest

    Hi Mike

    I would suggest that im in the 'VHDL - for intermediates' catergory,
    looking for bit of info on dual port ram.

    Since I very well could still be in the beginners group, could you
    explain what the templates are all about please?? I had already looked
    over the posts which come up under your suggested search string,
    previous to my original question, and most of those posts are talking
    about instantiating primitives, which is what I am doing..

    So the original questions in summary were along the lines of:

    Is there any particular issue with having the same clock - with no
    phase difference - going into both ports of the RAM??

    What is the worst thing that will happen if I am referencing the same
    address, but ONLY writing to one address at that time?? From the
    Xilinx info I would suggest that I will just get an unknown value on my
    read port..

    Thanks for your time

    Andrew
     
    dwerdna, Apr 4, 2005
    #3
  4. dwerdna wrote:

    > Since I very well could still be in the beginners group, could you
    > explain what the templates are all about please?? I had already looked
    > over the posts which come up under your suggested search string,
    > previous to my original question, and most of those posts are talking
    > about instantiating primitives, which is what I am doing..


    And others show template inference.
    Synthesis manuals also show RAM templates.

    > Is there any particular issue with having the same clock - with no
    > phase difference - going into both ports of the RAM??


    No. Make sure it is on a global net.

    > What is the worst thing that will happen if I am referencing the same
    > address, but ONLY writing to one address at that time?? From the
    > Xilinx info I would suggest that I will just get an unknown value on my
    > read port..


    I don't know. Consider arbitration.


    -- Mike Treseler
     
    Mike Treseler, Apr 4, 2005
    #4
  5. dwerdna

    Duane Clark Guest

    dwerdna wrote:
    >
    > What is the worst thing that will happen if I am referencing the same
    > address, but ONLY writing to one address at that time?? From the
    > Xilinx info I would suggest that I will just get an unknown value on my
    > read port..
    >


    The error message generated when this happens in VHDL simulation says
    (for example):

    # ** Warning: Memory Collision Error on RAMB16_S4_S4: at simulation
    time 92425 ns.
    # A read was performed on address fff (hex) of port B while a write was
    requested to the same address on Port A The write will be successful
    however the read value is unknown until the next CLKB cycle
    # Time: 92425 ns Iteration: 2 Instance:
    /bd_top/uut/data_buf_e/ram2_e/art_ram_g__7/art_ram_e

    So there you go. One of the most detailed warning messages I have ever
    seen ;)
     
    Duane Clark, Apr 4, 2005
    #5
  6. dwerdna

    dwerdna Guest

    Thanks for your help Mike and Duane
     
    dwerdna, Apr 5, 2005
    #6
  7. On 4 Apr 2005 00:53:26 -0700, "dwerdna" <> wrote:

    >What is the worst thing that will happen if I am referencing the same
    >address, but ONLY writing to one address at that time?? From the
    >Xilinx info I would suggest that I will just get an unknown value on my
    >read port..


    You could consider "write-forwarding" around the DPRAM: add an
    equality comparator that detects (write address)==(read address);
    if equal, read data is taken from the write data pins instead of
    from the RAM. Obviously the detailed timing needs a lot of
    care, but the basic idea is straightforward enough.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Apr 7, 2005
    #7
  8. dwerdna

    dwerdna Guest

    Thanks Jonathan, thats a good suggestion.

    I've solved my problem, so its all good, but I havent looked into why a
    read from an address which is being written to will produce "X" when
    you go by the principal that a register can be read the same time it is
    written to. I guess the "X" is just descriptive to say that the value
    might not be what you expect, and this would be a more likely case is
    the clocks were at different frequencies.

    Anyway just a point of interest, nothing more

    Thanks again
     
    dwerdna, Apr 8, 2005
    #8
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