Dual-Port RAM Simulation in ModelSim

Discussion in 'VHDL' started by Keith Blankenship, Jan 4, 2006.

  1. I'm trying to simulate dual-port RAM using a shared variable in ModelSim
    6.1b.

    When I isolate the dual-port RAM in its own test bench the behavior is
    correct. However, when incorporated into my larger design the behavior
    is strange. For instance, the stored data does not appear at the
    data_out port until the first cycle the (registered) address changes.

    Has anyone experienced this problem? Could this be a bug in ModelSim?

    Thanks,
    Keith
    Keith Blankenship, Jan 4, 2006
    #1
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  2. Keith Blankenship wrote:
    > I'm trying to simulate dual-port RAM using a shared variable in ModelSim
    > 6.1b.


    Are you using a block ram code template
    provided by the fpga vendor? I don't recall
    any such template that uses a shared variable.

    > For instance, the stored data does not appear at the
    > data_out port until the first cycle the (registered) address changes.


    That sounds normal for block ram.

    > Could this be a bug in ModelSim?


    Very unlikely.

    -- Mike Treseler
    Mike Treseler, Jan 4, 2006
    #2
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