dual ported RAM - different aspect ratio

Discussion in 'VHDL' started by digichip1@zorro.isa-geek.com, Mar 14, 2007.

  1. -geek.com

    -geek.com Guest

    Hi!

    Some time ago I've learned, that I can instantiate Xilinx Block-RAM in
    dual-ported mode using shared variables and two separate processes
    accessing those variables. Example:
    -------------------------
    architecture rtl of intarnalRAM is
    type rft is array((2**ADDR_BITS)-1 downto 0) of
    std_logic_vector(WORD_SIZE-1 downto 0);

    shared variable RAM: rft;
    begin

    RAM_PORT_A: process (clk)
    begin
    if (rising_edge(clk)) then
    if (wr = '1') then
    RAM(conv_integer(addr_y)) := input_y;
    else
    data_y <= RAM(conv_integer(addr_y));
    end if;
    end if;
    end process;

    RAM_PORT_B: process (clk)
    begin
    if (rising_edge(clk)) then
    if (wr_x = '1') then
    RAM(conv_integer(addr_x)) := input_x;
    else
    data_x <= RAM(conv_integer(addr_x));
    end if;
    end if;
    end process;

    end rtl;
    --------------------------------------

    When synthesizing it with Xilinx WEBpack, I've noticed, that report
    shows
    separate (although the same) memory aspect ratio for each port.

    So I have two questions:
    1. how to write a *generic* VHDL so, that it's clear (to any
    synthesizer/
    simulator), that I'm expressing a RAM with two ports of different
    aspect
    ratio each?
    2) how to write VHDL for Xilinx Spartan devices, to get their BlockRAM
    instantiated with ports A/B having different aspect ratio? Say: portA=
    8its x 256words, portB= 16bits x 128words ... into the same RAM array?

    I write the above as separate questions, since I take into account,
    that
    one or the other may not have a valid answer.... although I hope, that
    both have :)

    Thenx

    -R
    -geek.com, Mar 14, 2007
    #1
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  2. -geek.com

    -geek.com Guest

    On Mar 14, 2:30 pm, -geek.com wrote:
    > Hi!
    >
    > Some time ago I've learned, that I can instantiate Xilinx Block-RAM in
    > dual-ported mode using shared variables and two separate processes
    > accessing those variables. Example:


    I'm posting my own reply to my original post.... in frantic
    desperation. PLS HELP!

    There was no response to my original post. I'm not that proficient in
    VHDL to understand if the question was plain stupid, or if it was
    'rocket-science'.... or just not interesting to the general public.

    Pls. make a comment - should I search any further for a correct VHDL
    construct (for dual ported RAM with ports of different aspect ratios),
    or should I just drop it as this circuitry do not have a relevant VHDL
    expression.

    -RP
    -geek.com, Mar 15, 2007
    #2
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  3. On 14 Mar 2007 06:30:34 -0700, -geek.com wrote:

    >Hi!
    >
    >Some time ago I've learned, that I can instantiate Xilinx Block-RAM in
    >dual-ported mode using shared variables and two separate processes
    >accessing those variables. Example:


    This does not instantiate the RAM, it infers it.

    Instantiation would be to declare the Xilinx Unisims library in your
    design, and look there for an appropriate component, e.g. RAMB16S18S36,
    with the port widths you want, use that component in your design, and
    connect all the ports appropriately in the port map.

    Which only answers the second of your questions.

    - Brian
    Brian Drummond, Mar 15, 2007
    #3
  4. -geek.com wrote:

    > Some time ago I've learned, that I can instantiate Xilinx Block-RAM in
    > dual-ported mode using shared variables and two separate processes
    > accessing those variables. Example:
    > -------------------------
    > architecture rtl of intarnalRAM is
    > type rft is array((2**ADDR_BITS)-1 downto 0) of
    > std_logic_vector(WORD_SIZE-1 downto 0);
    >
    > shared variable RAM: rft;
    > begin
    >
    > RAM_PORT_A: process (clk)
    > begin
    > if (rising_edge(clk)) then
    > if (wr = '1') then
    > RAM(conv_integer(addr_y)) := input_y;
    > else
    > data_y <= RAM(conv_integer(addr_y));
    > end if;
    > end if;
    > end process;
    >
    > RAM_PORT_B: process (clk)
    > begin
    > if (rising_edge(clk)) then
    > if (wr_x = '1') then
    > RAM(conv_integer(addr_x)) := input_x;
    > else
    > data_x <= RAM(conv_integer(addr_x));
    > end if;
    > end if;
    > end process;
    >
    > end rtl;
    > --------------------------------------
    >
    > When synthesizing it with Xilinx WEBpack, I've noticed, that report
    > shows
    > separate (although the same) memory aspect ratio for each port.
    >
    > So I have two questions:
    > 1. how to write a *generic* VHDL so, that it's clear (to any
    > synthesizer/
    > simulator), that I'm expressing a RAM with two ports of different
    > aspect
    > ratio each?


    If the question is how to describe a port size
    with a generic constant, here's an example.

    http://home.comcast.net/~mike_treseler/sync_template.vhd

    If the question is will a particular synthesis tool find the
    correct Xilinx element for such a dual-port description
    with mismatched aspect ratio, all I can say is
    I don't know. Try it and see.

    -- Mike Treseler
    Mike Treseler, Mar 15, 2007
    #4
  5. -geek.com

    -geek.com Guest

    On Mar 15, 4:10 pm, Mike Treseler <> wrote:
    > -geek.com wrote:
    > > So I have two questions:
    > > 1. how to write a *generic* VHDL so, that it's clear (to any
    > > synthesizer/
    > > simulator), that I'm expressing a RAM with two ports of different
    > > aspect
    > > ratio each?

    >
    > If the question is how to describe a port size
    > with a generic constant, here's an example.
    >
    > http://home.comcast.net/~mike_treseler/sync_template.vhd


    Hmmmm. I'm afraid this one is out of my league. I don't really know
    how to work out my way from that template to the actual syntesizable
    code. Never before I've passes to my synthesize tool anything that I
    could call 'a template'.

    But may be the 'template' is just for me to use an editor :) and
    replicate the 'template' .... which is a definition of.... ??? a
    single port?

    Or should I just treat the template as 'entity definition', and in the
    higher level entity use it in 'generate' construct?

    I'm afraid I don't understand the answer :(

    To be more explicit about my understanding:

    In my example, I understand, that saying 'shared variable' I passes to
    the interpreter (to the synthesize tool), a semantics, that something
    'state-full' (variable, the RAM block) will be used by more then one
    process.... process being a 'view-port' into that 'state-full
    something' - e.g. process being a 'port' in RAM-memory nomenclature.
    This is dual-ported RAM.

    Now reading through the template you've provided I don't see any
    construct I can call 'this is my RAM', neither do I see anything that
    would allow me to 'read semantically': "OK, this is port definition".

    I'd appreciate if you could give me some guidance on how to glue up a
    'more or less complete' source from that template.

    > If the question is will a particular synthesis tool find the
    > correct Xilinx element for such a dual-port description
    > with mismatched aspect ratio, all I can say is
    > I don't know. Try it and see.


    I will - following Brian's advice I looked up Xilinx RAMB16S18S36
    component and for the design I'll use that. But my prime concern was
    to see how to express the dual-ported/dual-aspect RAM in VHDL.

    So, thenx. At least I know, that the thing is not so trivial as I
    thought it is.

    -- Rafał Pietrak
    -geek.com, Mar 15, 2007
    #5
  6. >> If the question is how to describe a port size
    >> with a generic constant, here's an example.
    >> http://home.comcast.net/~mike_treseler/sync_template.vhd


    -geek.com wrote:
    > Hmmmm. I'm afraid this one is out of my league. I don't really know
    > how to work out my way from that template to the actual syntesizable
    > code. Never before I've passes to my synthesize tool anything that I
    > could call 'a template'.


    The name of the example is irrelevant.
    My intent was only to show you how to pass
    a vector width using an entity generic constant.
    You would have to edit your model yourself
    if you want to try out the idea.

    -- Mike Treseler
    Mike Treseler, Mar 15, 2007
    #6
  7. -geek.com wrote:
    > On Mar 14, 2:30 pm, -geek.com wrote:
    >> Hi!
    >>
    >> Some time ago I've learned, that I can instantiate Xilinx Block-RAM in
    >> dual-ported mode using shared variables and two separate processes
    >> accessing those variables. Example:

    >
    > I'm posting my own reply to my original post.... in frantic
    > desperation. PLS HELP!
    >
    > There was no response to my original post. I'm not that proficient in
    > VHDL to understand if the question was plain stupid, or if it was
    > 'rocket-science'.... or just not interesting to the general public.


    I didn't answer at first because I
    could tell from the question that
    you were not ready for any answer
    that I could express in a few lines of text.
    This has now been confirmed.

    Next time consider refining the
    question by googling and trying
    a few things yourself first.

    -- Mike Treseler
    Mike Treseler, Mar 15, 2007
    #7
  8. -geek.com

    -geek.com Guest

    On Mar 15, 8:54 pm, Mike Treseler <> wrote:
    > -geek.com wrote:
    > > On Mar 14, 2:30 pm, -geek.com wrote:
    > >> Hi!

    >
    > >> Some time ago I've learned, that I can instantiate Xilinx Block-RAM in
    > >> dual-ported mode using shared variables and two separate processes
    > >> accessing those variables. Example:

    >
    > > I'm posting my own reply to my original post.... in frantic
    > > desperation. PLS HELP!

    >
    > > There was no response to my original post. I'm not that proficient in
    > > VHDL to understand if the question was plain stupid, or if it was
    > > 'rocket-science'.... or just not interesting to the general public.

    >
    > I didn't answer at first because I
    > could tell from the question that
    > you were not ready for any answer
    > that I could express in a few lines of text.


    I hoped I've put sufficiently large context (a code snippet in
    particular), that for someone who knows the subject it would be just
    'a touch of a pencil' - that you could add a line or two to my code to
    make its ports asymetric.

    > This has now been confirmed.


    Sadly so.

    > Next time consider refining the
    > question by googling and trying
    > a few things yourself first.


    But that was not too nice. Thank you.

    I did. Didn't spend a semester googling, but the few queries I did,
    didn't return anything meaningfull... at least to me. You seem
    forgetting, that not knowing how to ask gets you meaningless
    answers... unless there is a human on the other end who can read
    between the lines.... so my query went to the list when everything
    else failed. That helped.... to some extend.

    Regards,

    -R
    -geek.com, Mar 16, 2007
    #8
  9. -geek.com wrote:

    > I hoped I've put sufficiently large context (a code snippet in
    > particular), that for someone who knows the subject it would be just
    > 'a touch of a pencil' - that you could add a line or two to my code to
    > make its ports asymetric.


    If I had such an inference model in my bag
    of tricks, I would have pulled it out.
    Often the device vendor is first with
    that sort of code template. Synthesis vendors
    concentrate on the inferring special hardware
    that is common to several brands. For example
    the RAM process below with one read-only
    and one write-only port will
    work for both brand A and X block RAMs.

    ram_access : process (clk) is
    begin
    if rising_edge(clk) then
    if we = '1' then
    mem(to_integer(push_tail_ptr)) <= (data_i);
    end if; -- write date in
    data_q <= mem(to_integer(pop_head_ptr));
    -- read data out
    end if;
    end process ram_access;

    See "Block RAM FIFO" here
    http://home.comcast.net/~mike_treseler/ for details.

    Consider taking Brian's advice and
    instance the exact vendor block that you want
    instead of pushing harder on this rope.

    -- Mike Treseler
    Mike Treseler, Mar 16, 2007
    #9
  10. -geek.com

    Andy Peters Guest

    On Mar 15, 12:37 am, -geek.com wrote:
    > On Mar 14, 2:30 pm, -geek.com wrote:
    >
    > > Hi!

    >
    > > Some time ago I've learned, that I can instantiate Xilinx Block-RAM in
    > > dual-ported mode using shared variables and two separate processes
    > > accessing those variables. Example:

    >
    > I'm posting my own reply to my original post.... in frantic
    > desperation. PLS HELP!
    >
    > There was no response to my original post. I'm not that proficient in
    > VHDL to understand if the question was plain stupid, or if it was
    > 'rocket-science'.... or just not interesting to the general public.
    >
    > Pls. make a comment - should I search any further for a correct VHDL
    > construct (for dual ported RAM with ports of different aspect ratios),
    > or should I just drop it as this circuitry do not have a relevant VHDL
    > expression.


    The bad news is that with the current version of XST (9.1), you cannot
    infer dual-ports where the ports have different sizes. You must
    instantiate them from the library. RTFM.

    -a
    Andy Peters, Mar 19, 2007
    #10
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