Dummy question about bidiretional Bus

Discussion in 'VHDL' started by Bluette, Jun 24, 2010.

  1. Bluette

    Bluette

    Joined:
    Jun 24, 2010
    Messages:
    2
    Hi all,
    I'm new at this forum and at VHDL, so forgive my inexperience :D

    I have to design a bidirectional bus and my idea was following:

    Code (Text):
    library ieee;
    use ieee.std_logic_1164.all;

    entity three_state is port
            (enable : in std_logic;
             data: in std_logic;
             output : out std_logic );
    end three_state;

    architecture dataflow of three_state is
                               
        begin
        output <= data after 10 ns when enable = '1' else 'Z' after 10 ns; --- Assegnazione condizionata ---
       
       
    end dataflow;

    library ieee;
    use ieee.std_logic_1164.all;

    entity three_state_bidir is port
            (enable_dir : in std_logic;
             dataIn: inout std_logic;
             dataOut : inout std_logic );
    end three_state_bidir;

    architecture inout_gate of three_state_bidir is
        component tstate is port(enable : in std_logic; data: in std_logic; output : out std_logic );
        end component;
        component inv is port (in1: in std_logic; ou1: out std_logic);
        end component;
        for all: tstate use entity work.three_state(dataflow);
        for all: inv use entity work.not2(not_nor);  
           
        signal disable_dir: std_logic;

        --- Enable_dir = 1, abilita il trasferimento da dataIn a dataOut, enable_dir = 0 il contrario
        begin  
            tr1: tstate port map(enable_dir, dataIn, dataOut);
            tr2: tstate port map(disable_dir, dataOut, dataIn);
           
            abil: inv port map(enable_dir, disable_dir);     -- I segnali di abilitazione sono mutuamente esclusivi
           
                   
       
    end inout_gate;
    and I did following testbench:

    Code (Text):
    library ieee;
    use ieee.std_logic_1164.all;

    entity tb_tstate_bidir is
    end tb_tstate_bidir;

    architecture tb of tb_tstate_bidir is
        component three_state_bidir
        port(enable_dir : in std_logic;
             dataIn: inout std_logic;
             dataOut : inout std_logic );
    end component;

    signal my_dataI : std_logic;
    signal my_dataO : std_logic;
    signal my_dir: std_logic;

    signal my_result : std_logic;  

    type tk is record
        i : std_logic;                                   --- dato input  
        o: std_logic;                                    --- dato output
        d : std_logic;                                   --- direzione
       
    end record;


    -- Vettore di test --
    constant tabl : tk :=
        (i => '1', o => '0', d => '1');
       
    constant PropDelay : time := 20 ns;

    begin
        dut : three_state_bidir port map(
        enable_dir => my_dir,
        dataIn => my_dataI,
        dataOut => my_dataO);
       
           
        test: process  
          variable vec : tk;
          begin
           
                my_dir <= tabl.d;
               
                wait for 15 ns;
                my_dataI <= tabl.i;
                wait for 15 ns;  
               --my_dataO <= tabl.o;
                wait for 80 ns;
                   
           
        wait; -- sospende per sempre il processo
    end process test;
    end tb;
    All is ok if I comment line "my_dataO <= tabl.o;", but if I uncomment it the result is I get dataOut 'X'. I think it's a resolution problem for the signal...how could I avoid this? Where am I in wrong? Hope in some help from you!

    If any question, ask me: my language is newbie's one...be patient!
    Thanks for your attention :)
     
    Bluette, Jun 24, 2010
    #1
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  2. Bluette

    Bluette

    Joined:
    Jun 24, 2010
    Messages:
    2
    Me again

    Any help? It's very important to me...
     
    Bluette, Jun 26, 2010
    #2
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