dynamic inialization

Discussion in 'VHDL' started by ikbangesh, May 31, 2010.

  1. ikbangesh

    ikbangesh

    Joined:
    May 26, 2010
    Messages:
    2
    Hi VHLD folks
    I am new to this language, please dont mind for silly question if i put.
    How can i iniatize std_logic vector (ref_lin1) dynamically in UUT where col_to-1 is coming from test bench.

    if col_tot is 17 ,ref_lin1 is iniatilized to 17 1s and if it 31, in ref_lin1 , there should be 31 1s.

    if reset_i = '1' then
    ref_lin1(col_tot downto 0) :="111111111111111111";
    end if;

    some more question which has confused me
    can i take integer in ports and if i define range then would it take 32 bits or bits for that range?

    I am not able to access value of generic from one file(test banch) in another file (UUT)

    Thanks in advance
    ikbangesh, May 31, 2010
    #1
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  2. ikbangesh

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Try this:
    Code:
    ref_lin1(col_tot downto 0) := (others => '1');
    
    joris, May 31, 2010
    #2
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