dynamic power analysis for VHDL model

Discussion in 'VHDL' started by gigi00000, Nov 20, 2011.

  1. gigi00000

    gigi00000

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    Hi,
    I want to use my VHDL design to do power calculation in FPGA.Can anybody tell me how to do that by forcing different input signals?
    thanking you all.
     
    gigi00000, Nov 20, 2011
    #1
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