Dynamic Power Consumption Estimates/Comparison

Discussion in 'VHDL' started by moogyd, Oct 16, 2009.

  1. moogyd

    moogyd Guest

    Hi,

    I am currently comparing soft IP's for use in our next ASIC product.
    For the initial comparison, I will use power consumption estimates
    from the supplier (mW/MHz).

    The issue is that some vendors quote for 90nm, some 130nm and some of
    180nm.

    Does anybody have a very rough rule of thumb for relative dynamic
    power consumption for different technologies.

    e.g. On average, 0.5mA/MHz @ 130nm => 4 * 0.5mA/MHz @ 180nm.

    Thanks for any comments.

    Steven
    moogyd, Oct 16, 2009
    #1
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  2. moogyd

    gabor Guest

    On Oct 16, 10:54 am, moogyd <> wrote:
    > Hi,
    >
    > I am currently comparing soft IP's for use in our next ASIC product.
    > For the initial comparison, I will use power consumption estimates
    > from the supplier (mW/MHz).
    >
    > The issue is that some vendors quote for 90nm, some 130nm and some of
    > 180nm.
    >
    > Does anybody have a very rough rule of thumb for relative dynamic
    > power consumption for different technologies.
    >
    > e.g. On average, 0.5mA/MHz @ 130nm => 4 * 0.5mA/MHz @ 180nm.
    >
    > Thanks for any comments.
    >
    > Steven


    For the same number of transistors (you'd have to check if this is
    a good assumption when switching process nodes) the dynamic power
    will be proportional to V squared times the gate capacitance. Now
    V is easy enough to get (core voltage), but the gate capacitance is
    not necessarily something you can derive from the overall geometry.
    I would imagine you could get these numbers from your suppliers,
    though.
    gabor, Oct 16, 2009
    #2
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