Easy way to define lots of zeroes

[Peter Bluer]

Hi,

Please could someone help with the following:

I have an output on an entity which is a std_ulogic_vector(31 DOWNTO 0) and
is called data_out.
Within the VHDL I have a std_ulogic called c_store.
At one point I want to do data_out <= "0000000000000000000000000000000" &
c_store;
(so all zeroes apart from the lsb which is replaced by the value of
c_store).

Is there any better way of defining it so I don't have to put in all those
zeroes?

ie: somehow using OTHERS => '0' etc.

Hope this makes sense,

Thanks.

 

[jens]

Put this inside a process:

data_out <= (others => '0');
data_out(0) <= c_store;

I think this would work too (more generic):

data_out <= (others => '0');
data_out(c_store'range) <= c_store;

 

[Mark McDougall]

I have an output on an entity which is a std_ulogic_vector(31 DOWNTO
0) and is called data_out. Within the VHDL I have a std_ulogic called
c_store. At one point I want to do data_out <=
"0000000000000000000000000000000" & c_store; (so all zeroes apart
from the lsb which is replaced by the value of c_store).

Is there any better way of defining it so I don't have to put in all
those zeroes?

<http://www.codecomments.com/archive378-2005-10-659444.html>

 

[Thomas Stanka]

Hi,

Put this inside a process:

data_out <= (others => '0');
data_out(0) <= c_store;

maybe you should try
data_out <= (0 => c_store, others => '0');
to short your code by one statement . This should work even outside a
process.

bye Thomas

 

[Peter Bluer]

Thanks very much for all the replies.