edge detection using sobel

Discussion in 'VHDL' started by kumar9422, May 29, 2010.

  1. kumar9422

    kumar9422

    Joined:
    May 29, 2010
    Messages:
    1
    i m doing project in VHDL for real time image processing *edge detection* using sobel operator
    in this i have to write code inside the process can u please help me..
    i used to write sobel gradients and i have taken out pdata5 as output..
    as i have to take out p5 in mask

    and
    is there any solution using array type



    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity edge_sobel is
    generic ( PWIDTH : integer := 8);
    port (
    pclk_i : in std_logic;
    fsync_i : in std_logic;
    rsync_i : in std_logic;
    pData1 : in STD_LOGIC_VECTOR(pwidth-1 downto 0);
    pData2 : in STD_LOGIC_VECTOR(pwidth-1 downto 0);
    pData3 : in STD_LOGIC_VECTOR(pwidth-1 downto 0);
    pData4 : in STD_LOGIC_VECTOR(pwidth-1 downto 0);
    pData5 : in STD_LOGIC_VECTOR(pwidth-1 downto 0);
    pData6 : in STD_LOGIC_VECTOR(pwidth-1 downto 0);
    pData7 : in STD_LOGIC_VECTOR(pwidth-1 downto 0);
    pData8 : in STD_LOGIC_VECTOR(pwidth-1 downto 0);
    pData9 : in STD_LOGIC_VECTOR(pwidth-1 downto 0);

    fsync_o : out std_logic;
    rsync_o : out std_logic;
    pdata_o : out std_logic_vector(pwidth-1 downto 0)
    );

    end entity edge_sobel;

    architecture Behavioral of edge_sobel is

    begin
    dummy_edge_sobel: process (pclk_i)
    begin
    if (pclk_i'event and pclk_i = '1') then
    -- You are to change the part of the code to make it fulfill
    -- edge detection based on the Sobel operator.

    rsync_o <= rsync_i;
    fsync_o <= fsync_i;
    pdata_o <= pData5;

    end if; -- pclk_i
    end process dummy_edge_sobel;


    end Behavioral;


    .
    kumar9422, May 29, 2010
    #1
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