edif and vhdl files mixed

Discussion in 'VHDL' started by Frank, Oct 22, 2003.

  1. Frank

    Frank Guest

    Hi,

    I'm using the EDK 3.2 with ISE 5.2 and made some user logic which I want to
    integrate with a microblaze system. According to the documentation (User
    core templates reference guide) it's possible to add your user logic in the
    form of an edif file (instead of vhdl). But how to do this? When I try to
    add an edif file into my ISE project, it's giving errors. Do I have to make
    black boxes or something?

    Frank
    Frank, Oct 22, 2003
    #1
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  2. Frank

    MM Guest

    Assuming your top level is VHDL, you don't need to explicitly add the edif
    files to the design. Instead you need to set up the Macro Search Path in the
    implementation (more specifically, Translation) properties. That's how I do
    it anyway...

    /Mikhail



    "Frank" <> wrote in message
    news:3f96827f$0$50946$...
    > Hi,
    >
    > I'm using the EDK 3.2 with ISE 5.2 and made some user logic which I want

    to
    > integrate with a microblaze system. According to the documentation (User
    > core templates reference guide) it's possible to add your user logic in

    the
    > form of an edif file (instead of vhdl). But how to do this? When I try to
    > add an edif file into my ISE project, it's giving errors. Do I have to

    make
    > black boxes or something?
    >
    > Frank
    >
    >
    MM, Oct 22, 2003
    #2
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  3. Frank

    Frank Guest

    But how to do it in the "official" way. I found something about making an
    ..bbd file but I can't get it working.

    "MM" <> wrote in message
    news:bn63o8$tnosd$-berlin.de...
    > Assuming your top level is VHDL, you don't need to explicitly add the edif
    > files to the design. Instead you need to set up the Macro Search Path in

    the
    > implementation (more specifically, Translation) properties. That's how I

    do
    > it anyway...
    >
    > /Mikhail
    >
    >
    >
    > "Frank" <> wrote in message
    > news:3f96827f$0$50946$...
    > > Hi,
    > >
    > > I'm using the EDK 3.2 with ISE 5.2 and made some user logic which I want

    > to
    > > integrate with a microblaze system. According to the documentation (User
    > > core templates reference guide) it's possible to add your user logic in

    > the
    > > form of an edif file (instead of vhdl). But how to do this? When I try

    to
    > > add an edif file into my ISE project, it's giving errors. Do I have to

    > make
    > > black boxes or something?
    > >
    > > Frank
    > >
    > >

    >
    >
    Frank, Oct 22, 2003
    #3
  4. Frank

    MM Guest

    "Frank" <> wrote in message
    news:3f96a519$0$50952$...
    > But how to do it in the "official" way. I found something about making an
    > .bbd file but I can't get it working.


    Well, that's all I know... If you figure it out let the group know please.
    BTW, comp.arch.fpga would probably be a better place for this discussion...
    So, why don't you repost your question there?

    /Mikhail
    MM, Oct 22, 2003
    #4
  5. Frank

    Frank Guest

    Founded solution:

    you have to make a .bbd file and place it into the data directory and place
    the .edf file into a netlist directory (is at same level as the data and hdl
    directories). While generating a netlist, the .edf file is automatically
    copied into your implementation directory (but you have to use the STYLE
    option in the .mpd file).

    "MM" <> wrote in message
    news:bn6ede$t5g8d$-berlin.de...
    > "Frank" <> wrote in message
    > news:3f96a519$0$50952$...
    > > But how to do it in the "official" way. I found something about making

    an
    > > .bbd file but I can't get it working.

    >
    > Well, that's all I know... If you figure it out let the group know please.
    > BTW, comp.arch.fpga would probably be a better place for this

    discussion...
    > So, why don't you repost your question there?
    >
    > /Mikhail
    >
    >
    Frank, Oct 23, 2003
    #5
  6. Frank

    Duane Clark Guest

    Frank wrote:
    > Founded solution:
    >
    > you have to make a .bbd file and place it into the data directory and place
    > the .edf file into a netlist directory (is at same level as the data and hdl
    > directories). While generating a netlist, the .edf file is automatically
    > copied into your implementation directory (but you have to use the STYLE
    > option in the .mpd file).


    It is also generally possible to add an edif file as a blackbox, and
    avoid all those special files. For example, I used the UART that Xilinx
    provides only as a edif file like this:

    architecture synth of UART is
    component uart_tx is
    port ( din : in STD_LOGIC_VECTOR (7 downto 0);
    write : in STD_LOGIC;
    reset_buffer : in STD_LOGIC;
    en_16_x_baud : in STD_LOGIC;
    clk : in STD_LOGIC;
    serial_out : out STD_LOGIC;
    buffer_full : out STD_LOGIC);
    end component;

    -- Configuration specification, used only for simulation.
    -- For synthesis, we are using a uart core from Xilinx which is
    -- supplied only as an EDIF file. See uart_readme.txt and xapp223.pdf.
    -- For simulation, we are using a behavioral model from FSF, which is
    -- close enough. The enable does not seem to work quite the same,
    -- resulting in much faster transmission rates during simulation.
    --synopsys translate_off;
    for uart_tx_dev: uart_tx
    use entity work.TxUnit
    port map (
    Clk => clk,
    Reset => RESET,
    Enable => en_16_x_baud,
    LoadA => write,
    TxD => serial_out,
    Busy => buffer_full,
    DataI => din
    );
    --synopsys translate_on;


    -- XST black box declaration
    attribute box_type : string;
    attribute box_type of uart_tx: component is "black_box";
    begin
    uart_tx_dev: uart_tx
    port map(
    din => UDIN,
    write => UWRITE,
    reset_buffer => '0',
    en_16_x_baud => UCLK_P,
    clk => CLK,
    serial_out => DISPLAYD,
    buffer_full => UBUF_FULL
    );


    --
    My real email is akamail.com@dclark (or something like that).
    Duane Clark, Oct 23, 2003
    #6
  7. Frank wrote:

    > But how to do it in the "official" way. I found something about making an
    > .bbd file but I can't get it working.


    Be skeptical of documents revealing the "official" to do synthesis.
    Do as much as you can in your own source and minimize
    vendor specific attributes and files.

    In this case, all you should need to do is declare a
    component representing the .edf entity that
    the place and route knows about.
    This "unbound" component will be wired up
    during place and route.

    Here's a related example.

    -- ...
    component clock_lock
    PORT
    (
    inclock : IN STD_LOGIC ;
    clock0 : OUT STD_LOGIC
    );
    END component;

    begin

    clk_gen: clock_lock
    PORT map (
    clk,
    clk_lk
    );
    -- ...

    -- Mike Treseler
    Mike Treseler, Oct 23, 2003
    #7
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