Electronic Design Processes 2005: Call For Papers

Discussion in 'VHDL' started by b_kapoor@yahoo.com, Jan 25, 2005.

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    The Electronic Design Processes (EDP) Workshop provides a forum for a
    cross-section of the design community to discuss state-of-the-art
    electronic design processes and CAD methodologies. As the requirements
    and complexities of electronic design increase, past ad-hoc approaches
    to design processes are proving inadequate. The workshop focuses on the
    improvement of the overall design process, rather than on the functions
    of the individual tools themselves. The core audience of EDP consists
    of CAD system integrators and methodologists, academic researchers, and
    design team managers. (Note. Reception only on April 6th, talks will be
    given on April 7th and 8th.)


    Theme in 2005: Supporting "Super-Sized" Designs


    As we scale to 90, 65 and even 45nm technologies, the elements of the
    chip interact with each other more closely, but the "1 over
    deep-sub-micron" scaling prohibits some classic N2 solutions. How
    does your shop approach these problems? We solicit papers and proposals
    for special/panel sessions that shed light on the methodologies used
    for real current and future chip and system designs.
    Call For Papers:
    http://www.eda.org/edps/EDP-2005_02.htm
     
    , Jan 25, 2005
    #1
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