"else process" clause

Discussion in 'VHDL' started by bxbxb3, May 26, 2005.

  1. bxbxb3

    bxbxb3 Guest

    Hi,
    Is the code correct/allowed? Actually I am trying to write the first part
    in
    structural style to save clock cycles, the second part is process which is
    sequential.

    architecture x of x is
    begin
    u<="01" when (rst='0' and s="000") else
    u<="10" when (rst='0' and s="001") ELSE
    PROCESS(clk)
    begin
    if(clk'event and clk='1') then
    case state is
    when state0=>
    if (rst='0' and s="010") then
    u<="11";
    state<=state1;
    elsif (rst='1'and ="011") then
    u<="00";
    state<=state2;
    end if;

    when state1=>
    u<="01";
    state<=state0;

    when state2=>
    u<="10";
    state<=state0;
    end case;
    and if;
    end process;
    end x;


    I want the 'u' to assign values immediately when the first two conditions
    are true. If they
    are false then the 'u' must be assigned a perticular value in the first
    clock cycle and
    another in the next clock cycle.I want to ask whether "ELSE PROCESS"
    statement is correct,
    I have never seen such a clause in literature. Thanks for the help.
     
    bxbxb3, May 26, 2005
    #1
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  2. bxbxb3

    Neo Guest

    oops, your code is not legal. You cannot mix concurrent and procedural
    statements. ie, you cannot have a process in a "when.. else" or a "with
    select" construct. a process exits independently and cannot also be
    defined in another process. try to understand the semantics of vhdl
    before coding.
     
    Neo, May 26, 2005
    #2
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  3. bxbxb3 wrote:

    > Is the code correct/allowed?


    No - as Neo already stated, but very easy to fix:


    PROCESS(rst, s, clk)
    begin
    if (rst='0' and s="000") then
    u<="01";
    elsif (rst='0' and s="001") then
    u<="10";
    elsif(clk'event and clk='1') then
    case state is
    when state0=>
    if (rst='0' and s="010") then
    u<="11";
    state<=state1;
    elsif (rst='1'and ="011") then
    u<="00";
    state<=state2;
    end if;

    when state1=>
    u<="01";
    state<=state0;

    when state2=>
    u<="10";
    state<=state0;
    end case;
    and if;
    end process;


    But let me add something:
    * If I did the correction right, we now have 2 asynchronous set / reset
    AND rst and s are also used for synchronous signals assignments
    (in state0). Are you shure, that this is, what you want?
    * There is no "when others" in the case statement.

    Ralf
     
    Ralf Hildebrandt, May 26, 2005
    #3
  4. For synthesizable code you want each sequential signal to be assigned
    from a single process as Ralf has done. To be explicit I like to
    assign a default value before the case statement (as shown below) or
    using the others clause. Some argue that this is unnecessary, but I
    like to do it.

    This (defining a default value for process signals) is a necessary
    practice for defining a purely combinational logic process if you want
    to avoid latches in synthesis; however, in the case of combinational
    logic you would not assign the signal to itself or you would get a
    latch.

    Hope this helps.

    PROCESS(rst, s, clk)
    begin
    if (rst='0' and s="000") then
    u<="01";
    elsif (rst='0' and s="001") then
    u<="10";
    elsif(clk'event and clk='1') then
    state<=state;
    u<=u;
    case state is
    when state0=>
    if (rst='0' and s="010") then
    u<="11";
    state<=state1;
    elsif (rst='1'and ="011") then
    u<="00";
    state<=state2;
    end if;

    when state1=>
    u<="01";
    state<=state0;

    when state2=>
    u<="10";
    state<=state0;
    end case;
    and if;
    end process;



    Ralf Hildebrandt wrote:
    > bxbxb3 wrote:
    >
    > > Is the code correct/allowed?

    >
    > No - as Neo already stated, but very easy to fix:
    >
    >
    > PROCESS(rst, s, clk)
    > begin
    > if (rst='0' and s="000") then
    > u<="01";
    > elsif (rst='0' and s="001") then
    > u<="10";
    > elsif(clk'event and clk='1') then
    > case state is
    > when state0=>
    > if (rst='0' and s="010") then
    > u<="11";
    > state<=state1;
    > elsif (rst='1'and ="011") then
    > u<="00";
    > state<=state2;
    > end if;
    >
    > when state1=>
    > u<="01";
    > state<=state0;
    >
    > when state2=>
    > u<="10";
    > state<=state0;
    > end case;
    > and if;
    > end process;
    >
    >
    > But let me add something:
    > * If I did the correction right, we now have 2 asynchronous set / reset
    > AND rst and s are also used for synchronous signals assignments
    > (in state0). Are you shure, that this is, what you want?
    > * There is no "when others" in the case statement.
    >
    > Ralf
     
    combinational.logic $ soc-ip.com, May 27, 2005
    #4
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