Embeding pipeline stages to a recursive adder tree code

Discussion in 'VHDL' started by capitan, Sep 24, 2011.

  1. capitan

    capitan

    Joined:
    Sep 24, 2011
    Messages:
    2
    Hello all,

    I have written, synthesized and tested (behavioral simulation) a generic adder tree that receives a bit string of arbitrary length and computes the sum of all bits. I have used a recursive function. My code is the following:

    Problem is that such a combinatorial design has high latency, limiting my clock in the rest of my design. To reduce it, I would like to add pipeline stages, but I don't know how exactly to do it, given the code above. Functions are c like sequential structures so I don't know how to add flip flops. I have thought of constructing the adder tree in parts, calling the function as many times as my pipeline stages and squeeze ffs in between but I would like to know if there is a better/easier solution. Thanks in advance.

    ps: I'm using Xilinx ISE.
    capitan, Sep 24, 2011
    #1
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  2. capitan

    flymolo

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    Jun 2, 2011
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    I think you will get maximum performance with Xilinx Core generator.
    http://www.xilinx.com/support/documentation/ip_documentation/addsub_ds214.pdf
    If you want to keep it parameric, try to add input or output flip-flops.You can do it externallly to your entity.
    Synth. tool will likely distribute the logic between registers to obtain max frequency so you dont need to split your algorithm manually.
    I guess ISE does it (http://www.synthworks.com/papers/VHDL_RTL_Pipelined_Multiplier_MAPLD_2002_S_BW.pdf) slide #7.

    input ->| FF | -> | Your Logic | -> | FF | ->... -> | FF | -> output
    Last edited: Sep 24, 2011
    flymolo, Sep 24, 2011
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  3. capitan

    joris

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    Jan 29, 2009
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    I think you can do this by having the recursion on entity level instead of function level.
    In order to do this,
    • Move the code outside the function, into the architecture body
    • Replace variables with signals
    • use if-generate statements instead of (sequencial) if statements
    • instantiate recursively: instantiating AdderTree with adjusted input vector

    Now, if done correctly, at this point the code should yield exactly the same netlist.


    However, now a pipeline can be introduced (again using if-generate statements if required for fine-tuning)
    joris, Sep 24, 2011
    #3
  4. capitan

    capitan

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    Sep 24, 2011
    Messages:
    2
    Thanks for your replies. I was feeling lazy so I trusted XST to add the pipeline stages. My clock frequency went to 72MHz from 23Mhz. I'll keep your advice in mind jorris I haven't though of that (always thought recursion as having to call some function). I don't feel too comfortable using functions and procedures in vhdl anyways.
    capitan, Sep 25, 2011
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