[EN]&[IT] VHDL, memory hierarchy

Discussion in 'VHDL' started by peppeska, Oct 2, 2009.

  1. peppeska

    peppeska

    Joined:
    Oct 2, 2009
    Messages:
    1
    hi!

    I have to model a CPU in VHDL, I have done almost everything but I lack the memory to be developed ...

    this memory must be:
    - A memory hierarchy consisting of a single cache and main
    Memory

    - The cache is organized as direct mapped caches with victim cache. Suppose a policy of type write back.


    Could you advise me?
    maybe some sample code? it looks abbasstanza spelling and already 'developed but I can not find anything ...

    [IT]
    VHDL, gerarchia di memoria...

    salve!

    devo modellare una CPU in vhdl, ho fatto quasi tutto ma mi manca da sviluppare la memoria...

    questa memoria deve essere:
    - una gerarchia di memoria costituita da un’unica cache e dalla main
    memory

    - La cache è organizzata come cache direct mapped con victim cache. Si ipotizzi una politica di tipo
    write back.


    Potete darmi dei consigli? magari del codice di esempio? dovrebbe essere una cosa abbasstanza commune e gia' sviluppata ma non riesco a trovare nulla...
    peppeska, Oct 2, 2009
    #1
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  2. peppeska

    pato86

    Joined:
    Nov 2, 2009
    Messages:
    1
    Hi did you solve it? I have the same task to do and i cant find anything useful
    Someone else in this forum can help pls?

    Ciao, alla fine hai risolto? Ho lo stesso lavoro da sviluppare ma non riesco a trovare niente di utile.

    Qualcuno nel forum può aiutarmi??
    pato86, Nov 2, 2009
    #2
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