Enumeration types and bits

Discussion in 'VHDL' started by Pleg, Mar 7, 2006.

  1. Pleg

    Pleg Guest

    Let's say I've a proto board with a button; I don't know now if the wire
    connected to the button has a value of 1 when the button is high or when
    it's low, but I don't care: I'm using an enumerated type inside my VHDL
    code: "type button_state is (high, low);". But now I want to map that states
    "high", "low" to real "1", "0" so that I can use that button, linking it to
    my signals in the .ucf file.
    How do I do it? How can I map my enumerated type to binary 1,0s?


    Thanks,


    Pleg
     
    Pleg, Mar 7, 2006
    #1
    1. Advertising

  2. Pleg wrote:

    > How do I do it? How can I map my enumerated type to binary 1,0s?


    An std_ulogic bit might be a better choice in this case.
    I only use an enumerated type for internal registers
    when I don't care what what values synthesis picks for me.

    For example, with this code

    type TxState_t is (
    IDLE,
    START,
    SEND,
    STOP
    );
    variable TxState_v : TxState_t;

    I don't care if START becomes "01" "10" or "0001"
    as long as synthesis decodes it consistently.
    (it does)

    -- Mike Treseler
     
    Mike Treseler, Mar 7, 2006
    #2
    1. Advertising

  3. Pleg

    Pleg Guest

    > An std_ulogic bit might be a better choice in this case.
    > I only use an enumerated type for internal registers
    > when I don't care what what values synthesis picks for me.


    Yes I was afraid that the answer was something like this :)

    Thanks!



    Pleg
     
    Pleg, Mar 7, 2006
    #3
  4. Pleg

    Rob Dekker Guest

    Hi Pleg,

    Most synthesis tools support the attribute ENUM_ENCODING for this.
    It allows you to set the bit-encoding for the values of an enumerated type.

    For two states, that (encoding) is sort of a no-oops, but for more states it
    can and will make a difference (good or bad).

    Also note that synthesis tools choose a 'default' encoding scheme if you do
    not specify the enum_encoding attribute. The default differs per tool, and
    sometimes per target technology. FPGA synthesis tools often default to onehot encoding,
    while default 'binary' encoding is standard practice for ASICs.

    Rob


    "Pleg" <> wrote in message news:fzmPf.20492$...
    > Let's say I've a proto board with a button; I don't know now if the wire
    > connected to the button has a value of 1 when the button is high or when
    > it's low, but I don't care: I'm using an enumerated type inside my VHDL
    > code: "type button_state is (high, low);". But now I want to map that states
    > "high", "low" to real "1", "0" so that I can use that button, linking it to
    > my signals in the .ucf file.
    > How do I do it? How can I map my enumerated type to binary 1,0s?
    >
    >
    > Thanks,
    >
    >
    > Pleg
    >
    >
     
    Rob Dekker, Mar 8, 2006
    #4
  5. Pleg

    Pleg Guest

    Thanks to everybody!


    Pleg
     
    Pleg, Mar 10, 2006
    #5
  6. Pleg

    KJ Guest

    You can convert the std_logic to an integer and then use that as an input to
    the 'val attribute. Something like the code below (code is not totally
    correct, but should be close enough for you to work out the details).

    entity Top is....
    Button: std_logic;
    end Top;

    architecture RTL of Top is
    type button_state is (high, low);
    signal Button_Signal, Button_Signal2: button_state;

    -- Maybe make a function to do the conversion from std_logic to button
    type....hides the details of the conversion
    -- when you go to use it....on the other hand, this function probably
    only gets used in one place of the code anyway
    --
    function To_Button_State(L: std_logic) return button_state is
    variable RetVal: button_state;
    begin
    RetVal := button_state'val(to_integer(unsigned(L)));
    return(RetVal);
    end To_Button_State;
    begin
    -- Some like to see a simple type conversion function being called in
    the 'main' VHDL
    Button_Signal <= To_Button_State(Button);

    -- Or alternatively you could use....
    Button_Signal2 <= button_state'val(to_integer(unsigned(Button)));
    end RTL;

    "Pleg" <> wrote in message
    news:fzmPf.20492$...
    > Let's say I've a proto board with a button; I don't know now if the wire
    > connected to the button has a value of 1 when the button is high or when
    > it's low, but I don't care: I'm using an enumerated type inside my VHDL
    > code: "type button_state is (high, low);". But now I want to map that
    > states
    > "high", "low" to real "1", "0" so that I can use that button, linking it
    > to
    > my signals in the .ucf file.
    > How do I do it? How can I map my enumerated type to binary 1,0s?
    >
    >
    > Thanks,
    >
    >
    > Pleg
    >
    >
     
    KJ, Mar 10, 2006
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Charlie

    enumeration types

    Charlie, Feb 8, 2005, in forum: VHDL
    Replies:
    4
    Views:
    566
    Charlie
    Feb 9, 2005
  2. sarmin kho
    Replies:
    2
    Views:
    829
    A. Lloyd Flanagan
    Jun 15, 2004
  3. Markus Schickler

    Generating Enumeration Types at runtime

    Markus Schickler, May 4, 2007, in forum: Java
    Replies:
    5
    Views:
    525
    =?ISO-8859-1?Q?Arne_Vajh=F8j?=
    Jun 9, 2007
  4. puvit82
    Replies:
    4
    Views:
    763
    puvit82
    Feb 1, 2008
  5. Marcel Müller

    Extend enumeration types?

    Marcel Müller, Sep 13, 2009, in forum: C++
    Replies:
    4
    Views:
    1,069
    Pascal J. Bourguignon
    Sep 14, 2009
Loading...

Share This Page