EPP interface using Altera FPGA

Discussion in 'VHDL' started by Michele Bergo, Nov 5, 2004.

  1. I want to realize an EPP interface using Altera FPGA Cyclone (read and write
    operation) but I have some synchronization problems. I want to sample datas
    from a 4 bits chip, storing them in a ZBT SRAM memory (Flow trought) and
    later acquiring them by parallel port. the chip works at 10MHz but the pll
    on board can't divide input clock of 20MHz for 2. How can I divide the
    frequency?
    thanks. Does anyone do something like that?
     
    Michele Bergo, Nov 5, 2004
    #1
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  2. Michele Bergo wrote:


    > the chip works at 10MHz but the pll
    > on board can't divide input clock of 20MHz for 2. How can I divide the
    > frequency?


    Is it really so simple?

    process(reset,clk_in)
    begin
    if (reset='1') then
    clk_out='0'; -- or '1' - whatever you want
    elsif rising_edge(clk_in) then
    clk_out<=NOT(clk_out);
    end if;
    end process;

    If clk_out has to drive many cells, clock skew on the FPGA may be a
    problem. Therefore depending on the FPGA you may instantiate a clock
    buffer, that buffers clk_out. Read the manual for you FPGA how to do it.
    Often it will be a simple component that has to be instantiated with
    input clk_out.


    Ralf
     
    Ralf Hildebrandt, Nov 6, 2004
    #2
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  3. Thank u very much.

    "Ralf Hildebrandt" <> ha scritto nel messaggio
    news:...
    > Michele Bergo wrote:
    >
    >
    > > the chip works at 10MHz but the pll
    > > on board can't divide input clock of 20MHz for 2. How can I divide the
    > > frequency?

    >
    > Is it really so simple?
    >
    > process(reset,clk_in)
    > begin
    > if (reset='1') then
    > clk_out='0'; -- or '1' - whatever you want
    > elsif rising_edge(clk_in) then
    > clk_out<=NOT(clk_out);
    > end if;
    > end process;
    >
    > If clk_out has to drive many cells, clock skew on the FPGA may be a
    > problem. Therefore depending on the FPGA you may instantiate a clock
    > buffer, that buffers clk_out. Read the manual for you FPGA how to do it.
    > Often it will be a simple component that has to be instantiated with
    > input clk_out.
    >
    >
    > Ralf
     
    Michele Bergo, Nov 6, 2004
    #3
  4. Michele Bergo

    Yann KERNIN Guest

    Hi,

    I'm also interrested with the EPP protocol to develop it in a Xilinx FPGA.

    Something I don't know is what system manage the DIR pin of the
    interface chip (computer or FPGA). If, it is the FPGA, what are the
    timing concerning this signal.

    Thanks
    Yann

    Michele Bergo a écrit :
    > I want to realize an EPP interface using Altera FPGA Cyclone (read and write
    > operation) but I have some synchronization problems. I want to sample datas
    > from a 4 bits chip, storing them in a ZBT SRAM memory (Flow trought) and
    > later acquiring them by parallel port. the chip works at 10MHz but the pll
    > on board can't divide input clock of 20MHz for 2. How can I divide the
    > frequency?
    > thanks. Does anyone do something like that?
    >
    >
    >
     
    Yann KERNIN, Nov 26, 2004
    #4
  5. Yann KERNIN wrote:

    > I'm also interrested with the EPP protocol to develop it in a Xilinx FPGA.
    >
    > Something I don't know is what system manage the DIR pin of the
    > interface chip (computer or FPGA). If, it is the FPGA, what are the
    > timing concerning this signal.


    http://www.google.com/search?q=EPP signal definitions

    -- Mike Treseler
     
    Mike Treseler, Nov 26, 2004
    #5
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